EP1C20F400I7 Altera, EP1C20F400I7 Datasheet - Page 14
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EP1C20F400I7
Manufacturer Part Number
EP1C20F400I7
Description
IC CYCLONE FPGA 20K LE 400-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C20F400I7
Number Of Logic Elements/cells
20060
Number Of Labs/clbs
2006
Total Ram Bits
294912
Number Of I /o
301
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-FBGA
Family Name
Cyclone®
Number Of Logic Blocks/elements
20060
# I/os (max)
301
Frequency (max)
320.1MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
20060
Ram Bits
294912
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
400
Package Type
FBGA
No. Of Logic Blocks
2006
No. Of Macrocells
20060
Family Type
Cyclone
No. Of Speed Grades
7
No. Of I/o's
301
Clock Management
PLL
I/o Supply Voltage
4.1V
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1049
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C20F400I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1C20F400I7
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1C20F400I7N
Manufacturer:
ALTERA31
Quantity:
1 201
Part Number:
EP1C20F400I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Cyclone Device Handbook, Volume 1
Figure 2–6. LE in Normal Mode
Note to
(1)
2–8
Preliminary
addnsub (LAB Wide)
data1
data2
data3
cin (from cout
of previous LE)
data4
This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
Figure
(1)
2–6:
Register Feedback
preset/load, synchronous clear, synchronous load, and clock enable
control for the register. These LAB-wide signals are available in all LE
modes. The addnsub control signal is allowed in arithmetic mode.
The Quartus II software, in conjunction with parameterized functions
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, you can also
create special-purpose functions that specify which LE operating mode to
use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see
Quartus II Compiler automatically selects the carry-in or the data3
signal as one of the inputs to the LUT. Each LE can use LUT chain
connections to drive its combinatorial output directly to the next LE in the
LAB. Asynchronous load data for the register comes from the data3
input of the LE. LEs in normal mode support packed registers.
4-Input
LUT
Register chain
connection
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
sclear
(LAB Wide)
ADATA
ENA
D
ALD/PRE
aload
CLRN
Q
Figure
Altera Corporation
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
LUT chain
connection
Register
chain output
2–6). The
May 2008