EP4CE40F29C7N Altera, EP4CE40F29C7N Datasheet - Page 36
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EP4CE40F29C7N
Manufacturer Part Number
EP4CE40F29C7N
Description
IC CYCLONE IV E FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29C7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2685
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE40F29C7N
Manufacturer:
ALTERA
Quantity:
852
Part Number:
EP4CE40F29C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
1–36
Table 1–44. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices
Table 1–45. IOE Programmable Delay on Row Pins for Cyclone IV GX Devices
Cyclone IV Device Handbook, Volume 3
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output
register to output pin
Input delay from
dual-purpose clock pin
to fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output
register to output pin
Input delay from
dual-purpose clock pin
to fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software
Parameter
Parameter
Table
Table
1–44:
1–45:
Table 1–44
devices.
Pad to I/O
dataout to
core
Pad to I/O
input register
I/O output
register to
pad
Pad to global
clock network
Pad to I/O
dataout to
core
Pad to I/O
input register
I/O output
register to
pad
Pad to global
clock
network
Affected
Affected
Paths
Paths
and
Table 1–45
Settings
Settings
Number
Number
12
12
of
of
7
8
2
7
8
2
Offset
Offset
Min
Min
list the IOE programmable delay for Cyclone IV GX
0
0
0
0
0
0
0
0
1.314
1.313
0.461
0.712
1.313
1.312
0.438
0.713
Fast Corner
C6
Fast Corner
C6
1.210
1.208
0.421
0.682
1.209
1.208
0.404
0.682
I7
I7
(Note
2.209
2.205
0.789
1.225
2.184
2.200
0.751
1.228
(Note
C6
C6
Max Offset
Max Offset
1),
1), (2)—Preliminary
(2)
Chapter 1: Cyclone IV Device Datasheet
2.398
2.406
0.869
1.407
2.336
2.399
0.825
1.41
© December 2010 Altera Corporation
Slow Corner
Slow Corner
C7
C7
—Preliminary
2.526
2.563
0.933
1.562
2.451
2.554
0.886
1.566
C8
C8
Switching Characteristics
2.443
2.450
0.884
1.421
2.387
2.446
0.839
1.424
I7
I7
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns