EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 49
EP3C40F484C8N
Manufacturer Part Number
EP3C40F484C8N
Description
IC CYCLONE III FPGA 40K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C40F484C8N.pdf
(274 pages)
Specifications of EP3C40F484C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
331
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
331
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
2475
Family Type
Cyclone III
No. Of I/o's
331
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2492
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F484C8N
Manufacturer:
ALTERA
Quantity:
852
Verification
Figure 9. Physical Synthesis Optimizations
© November 2008 Altera Corporation
f
For more information, refer to the
in volume 2 of the Quartus II Handbook.
The Design Space Explorer (DSE) is a utility that automates the process of finding the
optimal collection of Quartus II software settings for your design. The Search for Best
Performance and Search for Best Area options under Exploration Settings, as in
Figure
improvements with multiple compilations.
10, use a predefined exploration space to target design performance or area
Netlist Optimizations and Physical Synthesis
chapter
Page 49