EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 139
EP3C40F484C8N
Manufacturer Part Number
EP3C40F484C8N
Description
IC CYCLONE III FPGA 40K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C40F484C8N.pdf
(274 pages)
Specifications of EP3C40F484C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
331
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
331
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
2475
Family Type
Cyclone III
No. Of I/o's
331
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2492
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F484C8N
Manufacturer:
ALTERA
Quantity:
852
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
True Output Buffer Feature
Figure 7–13. Differential HSTL Class II Interface
Note to
(1) PLL output clock pins do not support differential HSTL Class II I/O standard.
True Output Buffer Feature
Programmable Pre-Emphasis
Figure 7–14. The Output Signal with Pre-Emphasis
© December 2009
Figure
Output Buffer (1)
7–13:
Altera Corporation
Figure 7–13
Cyclone III device family true differential transmitters offer programmable
pre-emphasis—you can choose to turn it on or off. The default setting is on.
The programmable pre-emphasis boosts the high frequencies of the output signal to
compensate the frequency-dependant attenuation of the transmission line to
maximize the data eye opening at the far-end receiver. Without pre-emphasis, the
output current is limited by the V
transmitter. At high frequency, the slew rate may not be fast enough to reach full V
before the next edge; this may lead to pattern dependent jitter. With pre-emphasis, the
output current is momentarily boosted during switching to increase the output slew
rate. The overshoot produced by this extra switching current is different from the
overshoot caused by signal reflection. This overshoot happens only during switching,
and does not produce ringing.
Figure 7–14
shows the differential HSTL Class II interface.
shows the differential output signal with pre-emphasis.
Negative channel (n)
V
Positive channel (p)
TT
50 Ω
V
TT
50 Ω
Z 0 = 50 Ω
Z 0 = 50 Ω
OD
specification and the output impedance of the
V
TT
Overshoot
Undershoot
V
50 Ω
OD
V
TT
50 Ω
Cyclone III Device Handbook, Volume 1
Receiver
7–15
OD