EP1C20F324C8N Altera, EP1C20F324C8N Datasheet - Page 9
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EP1C20F324C8N
Manufacturer Part Number
EP1C20F324C8N
Description
IC CYCLONE FPGA 20K LE 324-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C20F324C8N
Number Of Logic Elements/cells
20060
Number Of Labs/clbs
2006
Total Ram Bits
294912
Number Of I /o
233
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone®
Number Of Logic Blocks/elements
20060
# I/os (max)
233
Frequency (max)
275.03MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
20060
Ram Bits
294912
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1798
EP1C20F324C8N
EP1C20F324C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C20F324C8N
Manufacturer:
ALTERA
Quantity:
453
Company:
Part Number:
EP1C20F324C8NGA
Manufacturer:
ALTERA
Quantity:
3 000
Logic Array
Blocks
Figure 2–2. Cyclone LAB Structure
Altera Corporation
May 2008
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, look-up table (LUT) chain, and register chain connection
lines. The local interconnect transfers signals between LEs in the same
LAB. LUT chain connections transfer the output of one LE's LUT to the
adjacent LE for fast sequential LUT connections within the same LAB.
Register chain connections transfer the output of one LE's register to the
adjacent LE's register within a LAB. The Quartus
associated logic within a LAB or adjacent LABs, allowing the use of local,
LUT chain, and register chain connections for performance and area
efficiency.
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM
blocks from the left and right can also drive a LAB's local interconnect
through the direct link connection. The direct link connection feature
minimizes the use of row and column interconnects, providing higher
Figure 2–2
LAB
details the Cyclone LAB.
Local Interconnect
Row Interconnect
®
II Compiler places
Logic Array Blocks
Column Interconnect
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Preliminary
2–3