EP3C25F256C8N Altera, EP3C25F256C8N Datasheet - Page 31
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EP3C25F256C8N
Manufacturer Part Number
EP3C25F256C8N
Description
IC CYCLONE III FPGA 25K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C25F256C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
156
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2077
EP3C25F256C8NES
EP3C25F256C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C25F256C8N
Manufacturer:
ALTERA
Quantity:
1
Part Number:
EP3C25F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
© January 2010 Altera Corporation
Table 1–29. Cyclone III Devices True LVDS Transmitter Timing Specifications
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications
of 2)
f
clock frequency)
HSIODR
t
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) True LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6).
(2) t
f
frequency)
HSIODR
t
HSC LK
DUTY
LOCK
HSC LK
DUTY
(2)
Symbol
Symbol
LOC K
(input clock
(input
Table
is the time required for the PLL to lock from the end of device configuration.
1–29:
Modes
Modes
×10
×10
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
10
10
10
10
10
10
80
70
40
20
10
45
C6
C6
402.5
402.5
Max
420
420
420
420
420
420
840
840
840
840
840
420
200
500
Max
320
320
320
320
320
640
640
640
640
640
55
55
1
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
10
10
10
10
10
10
80
70
40
20
10
45
C7, I7
C7, I7
402.5
402.5
402.5
402.5
Max
370
370
370
370
370
740
740
740
740
740
200
500
Max
320
320
320
320
320
640
640
640
640
640
55
55
1
Cyclone III Device Handbook, Volume 2
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
10
10
10
10
10
10
80
70
40
20
10
45
C8, A7
(Note 1)
C8, A7
(Note 1)
402.5
402.5
402.5
402.5
Max
320
320
320
320
320
640
640
640
640
640
200
550
Max
275
275
275
275
275
550
550
550
550
550
55
55
1
(Part 1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
%
ps
ps
%
1–21