EP3C16F484C7N Altera, EP3C16F484C7N Datasheet
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EP3C16F484C7N
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EP3C16F484C7N Summary of contents
Page 1
... The presence of all these conditions does not imply a bit error would necessarily occur. In addition, if some or all of the conditions are not present, the error will not occur. © June 2010 Altera Corporation ES-01020-3.0 Cyclone III Device Family ...
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... Table 2 lists the devices affected by the M9K memory read issue. Figure 1. Altera Data Code Marking Format Table 2. Affected Devices Device Cyclone III 65-nm: All devices ...
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... Class II I/O standard. (2) You must use a 200-MHz memory component speed grade. MSEL Pin Connection Altera has identified an issue with Cyclone III MSEL pins connected to V high CCIO the MSEL pins may be sensed at a different setting than was intended. The device might then require a power cycle to recover ...
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... I/O Power Static Current Issue Altera has identified an issue with static current in I/O banks powered at 3.3 Cyclone III EP3C25 Revision B and C and EP3C120 Revision A and B engineering sample devices. The affected devices might draw more current than expected as ...
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... Altera's standard warranty, San Jose, CA 95134 but reserves the right to make changes to any products and services at any time without notice. Altera assumes no www.altera.com responsibility or liability arising out of the application or use of any information, product, or service Technical Support described herein except as expressly agreed to in writing by Altera Corporation ...