EP1C12F256C8N Altera, EP1C12F256C8N Datasheet - Page 51

• Manufacturer Part Number: EP1C12F256C8N
• Description: IC CYCLONE FPGA 12K LE 256-FBGA
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C12F256C8N

• Number Of Logic Elements/cells: 12060
• Number Of Labs/clbs: 1206
• Total Ram Bits: 239616
• Number Of I /o: 185
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 12060
• # I/os (max): 185
• Frequency (max): 275.03MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 12060
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1791; EP1C12F256C8N

Figure 2–32. Cyclone IOE in Bidirectional I/O Configuration
Altera Corporation
May 2008
Column or Row
Interconect
ioe_clk[5..0]
comb_datain
data_in
Chip-Wide Reset
OE
clkout
aclr/prn
ce_in
ce_out
clkin
sclr/preset
The Cyclone device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinatorial logic may not require the
delay. Programmable delays decrease input-pin-to-logic-array and IOE
input register delays. The Quartus II Compiler can program these delays
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
ENA
PRN
ENA
PRN
ENA
Q
Q
Q
Pin Delay
Drive Strength Control
Output
Open-Drain Output
Slew Control
Input Register Delay
Logic Array Delay
Logic Array Delay
or Input Pin to
Input Pin to
Input Pin to
V
CCIO
V
CCIO
Optional
PCI Clamp
I/O Structure
Preliminary
Bus Hold
Programmable
Pull-Up
Resistor
2–45