EP3C16Q240C8N Altera, EP3C16Q240C8N Datasheet - Page 52
![IC CYCLONE III FPGA 16K 240PQFP](/photos/6/72/67260/544-240-pqfp_sml.jpg)
EP3C16Q240C8N
Manufacturer Part Number
EP3C16Q240C8N
Description
IC CYCLONE III FPGA 16K 240PQFP
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C16Q240C8N.pdf
(274 pages)
Specifications of EP3C16Q240C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
160
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
92
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2458
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16Q240C8N
Manufacturer:
ALTERA64
Quantity:
74
Page 52
f
f
In your TimeQuest SDC constraints file, use the following recommended constraints
as applicable to your design:
■
■
■
■
■
For more information on the SDC commands and clock uncertainties, refer to the
Quartus II TimeQuest Timing Analyzer
Device Resource Utilization Reports
After compilation, review the device resource utilization information to determine
that there is enough logic for any potential design change in future. If your
compilation results in a no-fit error, check the messages generated to understand what
causes the no-fit.
To determine resource usage, refer to the Flow Summary section of the Compilation
Report for a percentage representing the total logic utilization, which includes an
estimation of resources that cannot be used due to existing connections or logic use.
More detailed resource information is available by viewing the reports under
Resource Section in the Fitter section of the Compilation Report. There are also
reports that describe some of the optimizations that occurred during compilation. For
example, if you are using Quartus II integrated synthesis, the reports under the
Optimization Results folder in the Analysis & Synthesis section describe
information including registers that were removed during synthesis. This report can
be useful when estimating device resource utilization for a partial design, to ensure
that registers were not removed due to missing connections with other parts of the
design.
Quartus II Messages
Each stage of the compilation flow generates messages, including informational notes,
warnings, critical warnings and errors. Review these messages to check for any
potential design problems. To understand the meaning of the messages, right click on
the message and select Help. The Quartus II Help shows the meaning of the message.
For more information about messages and message suppression, refer to the
Quartus II Projects
create_clock, create_generated_clock – specify the frequencies and
relationships for all clocks in your design.
derive_pll_clocks – creates generated clocks for all PLL outputs, according
to the settings in the PLL megafunctions. Specify multicycle relationships for
LVDS transmitters or receiver deserialization factors.
set_input_delay, set_output_delay – specify external device or board
timing parameters.
derive_clock_uncertainty – automatically applies inter-clock, intra-clock,
and I/O interface uncertainties. You can also user the set_clock_uncertainty
constraint to specify clock uncertainty or skew for clocks or clock-to-clock
transfers.
check_timing – generates a report on any problem with the design or applied
constraints, including missing constraints.
chapter in volume 2 of the Quartus II Handbook.
chapter in volume 3 of the Quartus II Handbook.
© November 2008 Altera Corporation
Managing
Verification