EP4CE10E22C8LN Altera, EP4CE10E22C8LN Datasheet - Page 9

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EP4CE10E22C8LN

Manufacturer Part Number
EP4CE10E22C8LN
Description
IC CYCLONE IV FPGA 10K 144EQFP
Manufacturer
Altera
Series
CYCLONE® IV Er

Specifications of EP4CE10E22C8LN

Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
414000
Number Of I /o
91
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-EQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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External Memory Specification for DDR2 SDRAM
External Memory Specification for DDR2 SDRAM
Table 5. Full-Rate DDR2 SDRAM Support for Cyclone IV E Core Voltage 1.0-V Devices
March 2011 Altera Corporation
DDR2 SDRAM
Note to
(1) You must use the 267-MHz memory device speed grade to achieve the maximum clock rate.
Table
Memory Standard
5:
In the Quartus II software version 10.0, the Cyclone IV E I8L speed grade supported
full-rate DDR2 SDRAM with a maximum clock rate of up to 150 MHz on column and
row I/Os. This maximum clock rate is a preliminary specification pending the
finalization of the timing model.
In the Quartus II software version 10.0 SP1 and later, the Cyclone IV E I8L speed
grade full-rate DDR2 SDRAM maximum clock rate specification on column and row
I/Os has been revised due to the finalization of the timing model for the Cyclone IV E
device family.
Designs that already use the affected devices running full-rate DDR2 SDRAM at the
old maximum clock rate and pass timing in the Quartus II software version 10.0 SP1
and later run acceptably at the old frequencies—provided that the board settings
panel in the IP MegaWizard Plug-In Manager is populated accurately and the board
trace models representative of the relevant system are correctly entered in the
Pin Planner.
Core Voltage
Cyclone IV E
Table 5
Device
1.0 V
lists the current specification.
Speed Grade
I8L
Maximum Clock Rate (MHz)
Column and Row I/O
Single Chip Select
133
Errata Sheet for Cyclone IV Devices
(1)
Page 9

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