EP3C10F256C8N Altera, EP3C10F256C8N Datasheet - Page 107
![IC CYCLONE III FPGA 10K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP3C10F256C8N
Manufacturer Part Number
EP3C10F256C8N
Description
IC CYCLONE III FPGA 10K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C10F256C8N.pdf
(274 pages)
Specifications of EP3C10F256C8N
Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
182
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
No. Of Logic Blocks
645
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2417
EP3C10F256C8N
EP3C10F256C8N
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Manufacturer
Quantity
Price
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- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C10F256C8N PDF datasheet #7
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Chapter 6: I/O Features in the Cyclone III Device Family
OCT Support
LVDS Transmitter Programmable Pre-Emphasis
OCT Support
Table 6–3. Selectable I/O Drivers for On-Chip Series Termination with and Without Calibration Setting (Part 1 of 2)
© December 2009
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
I/O Standard
f
1
Altera Corporation
The Cyclone III device family true LVDS transmitter supports programmable
pre-emphasis. Programmable pre-emphasis is used to compensate the
frequency-dependent attenuation of the transmission line. It increases the amplitude
of the high-frequency components of the output signal, which cancels out much of the
high-frequency loss of the transmission line.
The Quartus II software allows two settings for programmable pre-emphasis
control—0 and 1, in which 0 is pre-emphasis off and 1 is pre-emphasis on. The default
setting is 1. The amount of pre-emphasis needed depends on the amplification of the
high-frequency components along the transmission line. You must adjust the setting
to suit your designs, as pre-emphasis decreases the amplitude of the low-frequency
component of the output signal as well.
For more information about the Cyclone III device family high-speed differential
interface support, refer to the
chapter.
The Cyclone III device family features OCT to provide I/O impedance matching and
termination capabilities. OCT helps to prevent reflections and maintain signal
integrity while minimizing the need for external resistors in high pin-count ball grid
array (BGA) packages. The Cyclone III device family provides I/O driver on-chip
impedance matching and on-chip series termination for single-ended outputs and
bidirectional pins.
When using on-chip series termination, programmable current strength is not
available.
There are two ways to implement OCT in the Cyclone III device family:
■
■
Table 6–3
termination.
On-Chip Series Termination with Calibration
OCT with calibration
OCT without calibration
Row I/O
50, 25
50, 25
50, 25
50, 25
lists the I/O standards that support impedance matching and series
50
50
25
Setting, in ohms (Ω)
Column I/O
50, 25
50, 25
50, 25
50, 25
50, 25
High-Speed Differential Interfaces in Cyclone III Devices
50
25
On-Chip Series Termination Without Calibration
Row I/O
50, 25
50, 25
50, 25
50, 25
50
50
25
Setting, in ohms (Ω)
Cyclone III Device Handbook, Volume 1
Column I/O
50, 25
50, 25
50, 25
50, 25
50, 25
50
25
6–7
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