EP1C6Q240C7N Altera, EP1C6Q240C7N Datasheet - Page 28
![IC CYCLONE FPGA 5980 LE 240-PQFP](/photos/6/72/67260/544-240-pqfp_sml.jpg)
EP1C6Q240C7N
Manufacturer Part Number
EP1C6Q240C7N
Description
IC CYCLONE FPGA 5980 LE 240-PQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C6Q240C7N
Number Of Logic Elements/cells
5980
Number Of Labs/clbs
598
Total Ram Bits
92160
Number Of I /o
185
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
No. Of Logic Blocks
598
No. Of Macrocells
5980
Family Type
Cyclone
No. Of Speed Grades
7
No. Of I/o's
185
Clock Management
PLL
I/o Supply Voltage
3.3V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1812
EP1C6Q240C7N
EP1C6Q240C7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C6Q240C7N
Manufacturer:
ALTERA
Quantity:
9
Part Number:
EP1C6Q240C7N
Manufacturer:
ALTERA
Quantity:
20 000
Cyclone Device Handbook, Volume 1
2–22
Preliminary
4K
2K
1K
512
256
128
512
256
128
4K
2K
1K
512
256
512
256
Table 2–3. M4K RAM Block Configurations (Simple Dual-Port)
Table 2–4. M4K RAM Block Configurations (True Dual-Port)
Read Port
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
2
4
1
2
4
8
16
32
9
18
36
8
16
9
18
Port A
4K × 1 2K × 2 1K × 4 512 × 8
v
v
v
v
v
v
—
—
—
4K × 1
v
v
v
v
v
v
—
—
—
is not available in the true dual-port mode. Mixed-width configurations
are also possible, allowing different read and write widths.
and
When the M4K RAM block is configured as a shift register block, you can
create a shift register up to 4,608 bits (w × m × n).
v
v
v
v
v
—
—
2–4
v
v
v
v
v
v
—
—
—
summarize the possible M4K RAM block configurations.
2K × 2
v
v
v
v
v
—
—
v
v
v
v
v
v
—
—
—
1K × 4
v
v
v
v
v
—
—
256 × 16
Write Port
v
v
v
v
v
v
—
—
—
512 × 8
Port B
v
v
v
v
v
—
—
128 × 32
v
v
v
v
v
v
—
—
—
256 × 16
v
v
v
v
v
—
—
512 × 9 256 × 18 128 × 36
v
v
v
—
—
—
—
—
—
512 × 9
Altera Corporation
v
v
—
—
—
—
—
v
v
v
—
—
—
—
—
—
Tables 2–3
256 × 18
May 2008
v
v
—
—
—
—
—
v
v
v
—
—
—
—
—
—