EP1K10FC256-3N Altera, EP1K10FC256-3N Datasheet - Page 56
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EP1K10FC256-3N
Manufacturer Part Number
EP1K10FC256-3N
Description
IC ACEX 1K FPGA 10K 256-FBGA
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K10FC256-3N
Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
136
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
256-FBGA
Family Name
ACEX™ 1K
Number Of Usable Gates
10000
Number Of Logic Blocks/elements
576
# I/os (max)
136
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
576
Ram Bits
12288
Device System Gates
56000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
ACEX 1K Programmable Logic Device Family Data Sheet
56
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t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EABDATA1
EABDATA2
EABWE1
EABWE2
EABRE1
EABRE2
EABCLK
EABCO
EABBYPASS
EABSU
EABH
EABCLR
AA
WP
RP
WDSU
WDH
WASU
WAH
RASU
RAH
WO
DD
EABOUT
EABCH
EABCL
Table 24. EAB Timing Microparameters
Symbol
Data or address delay to EAB for combinatorial input
Data or address delay to EAB for registered input
Write enable delay to EAB for combinatorial input
Write enable delay to EAB for registered input
Read enable delay to EAB for combinatorial input
Read enable delay to EAB for registered input
EAB register clock delay
EAB register clock-to-output delay
Bypass register delay
EAB register setup time before clock
EAB register hold time after clock
EAB register asynchronous clear time to output delay
Address access delay (including the read enable to output delay)
Write pulse width
Read pulse width
Data setup time before falling edge of write pulse
Data hold time after falling edge of write pulse
Address setup time before rising edge of write pulse
Address hold time after falling edge of write pulse
Address setup time before rising edge of read pulse
Address hold time after falling edge of read pulse
Write enable to data output valid delay
Data-in to data-out valid delay
Data-out delay
Clock high time
Clock low time
Note (1)
Parameter
Altera Corporation
(5)
(5)
(5)
(5)
Conditions