XC4005-5PQ208C Xilinx Inc, XC4005-5PQ208C Datasheet - Page 28

• Manufacturer Part Number: XC4005-5PQ208C
• Description: IC LOGIC CL ARRAY 5000GAT 208PQ
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005-5PQ208C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1069

XC4000, XC4000A, XC4000H Logic Cell Array Families
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the LCA device(s). The serial configuration
bitstream must be available at the DIN input of the lead
LCA device a short set-up time before each rising CCLK
edge. The lead LCA device then presents the preamble
data (and all data that overflows the lead device) on its
DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising CCLK edge.
How to Delay Configuration After Power-Up
There are two methods to delay configuration after power-
up: Put a logic Low on the PROGRAM input, or pull the
bidirectional INIT pin Low, using an open-collector (open-
drain) driver. (See also Figure 20 on page 2-27.)
RESET
COMPUTER
PORT
MICRO
I/O
STRB
D0
D1
D2
D3
D4
D5
D6
D7
+5 V
+5 V
INIT
DONE
CCLK
DIN
PROGRAM
M0
XC4000
M1
I/O PINS
OTHER
2-34
M2
DOUT
HDC
LDC
A Low on the PROGRAM input is the more radical ap-
proach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the XC4000 device keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration, causes the LCA
device to wait after having completed the configuration
memory clear operation. When INIT is no longer held Low
externally, the device determines its configuration mode
by capturing its status inputs, and is ready to start the
configuration process. A master device waits an additional
max 250 s to make sure that all slaves in the potential
daisy-chain have seen INIT being High.
•
•
•
TO CCLK OF OPTIONAL
DAISY-CHAINED LCA DEVICES WITH
DIFFERENT CONFIGURATIONS
TO DIN OF OPTIONAL
DAISY-CHAINED LCA DEVICES
WITH DIFFERENT CONFIGURATIONS
TO DIN OF OPTIONAL
SLAVE LCA DEVICES WITH
IDENTICAL CONFIGURATION
TO CCLK OF OPTIONAL
SLAVE LCA DEVICES WITH
IDENTICAL CONFIGURATION
X3393