XCS40XL-5PQG208C Xilinx Inc, XCS40XL-5PQG208C Datasheet - Page 45
![IC SPARTAN-XL FPGA 40K 208-PQFP](/photos/6/71/67100/pq208_sml.jpg)
XCS40XL-5PQG208C
Manufacturer Part Number
XCS40XL-5PQG208C
Description
IC SPARTAN-XL FPGA 40K 208-PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-XLr
Datasheet
1.XCS05XL-4VQG100C.pdf
(83 pages)
Specifications of XCS40XL-5PQG208C
Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
169
Number Of Gates
40000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1301
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCS40XL-5PQG208C
Manufacturer:
XILINX
Quantity:
656
Part Number:
XCS40XL-5PQG208C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
DS060 (v1.8) June 26, 2008
Product Specification
Notes:
1.
Write Operation
Read Operation
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
WCTS
WHTS
WOTS
T
WPTS
AHTS
WSTS
ASTS
DSTS
DHTS
WCS
WHS
WOS
IHCK
WPS
AHS
WSS
ASS
DSS
DHS
RCT
Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
IHO
ILO
ICK
RC
R
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Address read cycle time
Data valid after address change (no Write
Enable)
Address setup time before clock K
Single Port RAM
www.xilinx.com
Size
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
are expressed in nanoseconds unless otherwise noted.
(1)
Spartan and Spartan-XL FPGA Families Data Sheet
Min
8.0
8.0
4.0
4.0
1.5
1.5
0.0
0.0
1.5
1.5
0.0
0.0
1.5
1.5
0.0
0.0
2.6
3.8
1.8
2.9
-
-
-
-
-4
Max
6.5
7.0
1.2
2.0
Speed Grade
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
11.6
11.6
Min
5.8
5.8
2.0
2.0
0.0
0.0
2.7
1.7
0.0
0.0
1.6
1.6
0.0
0.0
2.6
3.8
2.4
3.9
-
-
-
-
-3
Max
7.9
9.3
1.6
2.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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