EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 234

• Manufacturer Part Number: EP2S60F484I4N
• Description: IC STRATIX II FPGA 60K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F484I4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 334
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 334
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1910; EP2S60F484I4N

Document Revision History
5–98
Stratix II Device Handbook, Volume 1
August, 2006,
v4.2
April 2006, v4.1
December 2005,
v4.0
July 2005, v3.1
May 2005, v3.0
March 2005,
v2.2
January 2005,
v2.1
Table 5–103. Document Revision History (Part 2 of 3)
Document
Date and
Version
Updated Table 5–73, Table 5–75, Table 5–77,
Table 5–78, Table 5–79, Table 5–81, Table 5–85, and
Table 5–87.
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Updated tables in “Internal Timing Parameters”
section.
Updated input rise and fall time.
Updated Table 5–3.
Updated Table 5–11.
Updated Figures 5–8 and 5–9.
Added parallel on-chip termination information to
“On-Chip Termination Specifications” section.
Updated Tables 5–28, 5–30,5–31, and 5–34.
Updated Table 5–78, Tables 5–81 through 5–90,
and Tables 5–92, 5–93, and 5–98.
Updated “PLL Timing Specifications” section.
Updated “External Memory Interface
Specifications” section.
Added Tables 5–95 and 5–101.
Updated “JTAG Timing Specifications” section,
including Figure 5–10 and Table 5–102.
Updated “External Memory Interface
Specifications” section.
Updated timing numbers throughout chapter.
Updated HyperTransport technology information in
Table 5–13.
Updated “Timing Model” section.
Updated “PLL Timing Specifications” section.
Updated “External Memory Interface
Specifications” section.
Updated tables throughout chapter.
Updated “Power Consumption” section.
Added various tables.
Replaced “Maximum Input & Output Clock Rate”
section with “Maximum Input & Output Clock Toggle
Rate” section.
Added “Duty Cycle Distortion” section.
Added “External Memory Interface Specifications”
section.
Changes Made
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Changed 0.2 MHz to 2 MHz in
Table 5–93.
Added new spec for half period
jitter (Table 5–101).
Added support for PLL clock
switchover for industrial
temperature range.
Changed f
4 MHz to 2 MHz in Table 5–92.
Fixed typo in t
specification in Table 5–92.
Updated V
specifications in Table 5–28.
Updated minimum values for t
t
Update maximum values for t
t
J C L
J P Z X
, and t
Summary of Changes
, and t
I N P F D
J P S U
D I F
J P X Z
Altera Corporation
O U T J I T T E R
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AC & DC max
in Table 5–102.
(min) spec from
in Table 5–102.
April 2011
J P C O
J C H
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