EP2S30F484C5N Altera, EP2S30F484C5N Datasheet - Page 148
EP2S30F484C5N
Manufacturer Part Number
EP2S30F484C5N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
342
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
342
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
484
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1892
EP2S30F484C5N
EP2S30F484C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F484C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Operating Conditions
5–12
Stratix II Device Handbook, Volume 1
Note to
(1)
Note to
(1)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Table 5–19. SSTL-2 Class I Specifications
Table 5–20. SSTL-2 Class II Specifications
Symbol
Symbol
CCIO
TT
REF
IH
IL
I H
I L
OH
OL
CCIO
TT
REF
IH
IL
I H
I L
OH
OL
(DC)
(DC)
(DC)
(DC)
(AC)
(AC)
(AC)
(AC)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table
Table
Output supply voltage
Termination voltage
Reference voltage
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
High-level output voltage
Low-level output voltage
Output supply voltage
Termination voltage
Reference voltage
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
High-level output voltage
Low-level output voltage
5–19:
5–20:
Parameter
Parameter
I
I
I
I
OH
OL
OH
OL
= 8.1 mA
= 16.4 mA
Conditions
= –8.1 mA
Conditions
= –16.4 mA
(1)
(1)
(1)
(1)
V
V
V
V
V
V
V
V
Minimum
Minimum
R E F
R E F
REF
REF
REF
REF
TT
TT
2.375
1.188
–0.30
2.375
1.188
–0.30
+ 0.57
+ 0.76
– 0.04
+ 0.18
– 0.04
+ 0.18
+ 0.35
+ 0.35
Typical
Typical
2.500
1.250
2.500
1.250
V
V
REF
REF
Altera Corporation
V
V
V
V
V
V
V
V
V
Maximum
Maximum
CCIO
R E F
R E F
REF
REF
REF
REF
TT
TT
2.625
1.313
2.625
1.313
3.00
– 0.57
– 0.76
+ 0.04
– 0.18
+ 0.04
– 0.18
+ 0.30
- 0.35
- 0.35
April 2011
Unit
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V