EP2S15F672C3 Altera, EP2S15F672C3 Datasheet - Page 157

• Manufacturer Part Number: EP2S15F672C3
• Description: IC STRATIX II FPGA 15K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S15F672C3

• Number Of Logic Elements/cells: 15600
• Number Of Labs/clbs: 780
• Total Ram Bits: 419328
• Number Of I /o: 366
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1879; EP2S15F672C3

Altera Corporation
April 2011
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum
voltage, and maximum temperature for input register setup time (t
and hold time (t
to calculate t
Figure 5–3
Table 5–33. Stratix II Device Timing Model Status
t
t
SU
H
= – data delay from input pin to input register
EP2S130
EP2S180
= + data delay from input pin to input register
EP2S15
EP2S30
EP2S60
EP2S90
Device
+ micro setup time of the input register
– clock delay from input pin to input register
+ micro hold time of the input register
+ clock delay from input pin to input register
shows the setup and hold timing diagram for input registers.
SU
and t
H
). The Quartus II software uses the following equations
H
timing for Stratix II devices input signals.
Preliminary
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Final
v
v
v
v
v
v
SU
5–21
)