EP2C20F256I8N Altera, EP2C20F256I8N Datasheet - Page 51

• Manufacturer Part Number: EP2C20F256I8N
• Description: IC CYCLONE II FPGA 20K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C20F256I8N

• Number Of Logic Elements/cells: 18752
• Number Of Labs/clbs: 1172
• Total Ram Bits: 239616
• Number Of I /o: 152
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 18752
• # I/os (max): 152
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 18752
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2103

Figure 2–21. Row I/O Block Connection to the Interconnect
Notes to
(1)
(2)
Altera Corporation
February 2007
The 35 data and control signals consist of five data out lines, io_dataout[4..0], five output enables,
io_coe[4..0], five input clock enables, io_cce_in[4..0], five output clock enables, io_cce_out[4..0],
five clocks, io_cclk[4..0], five asynchronous clear signals, io_caclr[4..0], and five synchronous clear
signals, io_csclr[4..0].
Each of the five IOEs in the row I/O block can have two io_datain (combinational or registered) inputs.
LAB Local
Interconnect
R4 & R24 Interconnects
Figure
to Adjacent LAB
Interconnect
Direct Link
2–21:
LAB
io_datain0[4..0]
io_datain1[4..0] (2)
C4 Interconnects
from Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
io_clk[5..0]
35
Cyclone II Device Handbook, Volume 1
I/O Block
Contains up to
Row I/O Block
Row
Five IOEs
Cyclone II Architecture
35 Data and
Control Signals
from Logic Array (1)
2–39