EP1K30FC256-2 Altera, EP1K30FC256-2 Datasheet - Page 58
![IC ACEX 1K FPGA 30K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP1K30FC256-2
Manufacturer Part Number
EP1K30FC256-2
Description
IC ACEX 1K FPGA 30K 256-FBGA
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K30FC256-2
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
171
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1831
EP1K30FC256-2
EP1K30FC256-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1K30FC256-2
Manufacturer:
ALTERA
Quantity:
6
Company:
Part Number:
EP1K30FC256-2
Manufacturer:
ALTERA30
Quantity:
70
ACEX 1K Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
58
t
t
t
t
t
t
t
t
t
t
t
t
t
DIN2IOE
DIN2LE
DIN2DATA
DCLK2IOE
DCLK2LE
SAMELAB
SAMEROW
SAMECOLUMN
DIFFROW
TWOROWS
LEPERIPH
LABCARRY
LABCASC
Table 26. Interconnect Timing Microparameters
Symbol
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
Operating conditions: V
Operating conditions: V
Operating conditions: V
Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
Delay from dedicated input pin to IOE control input
Delay from dedicated input pin to LE or EAB control input
Delay from dedicated input or clock to LE or EAB data
Delay from dedicated clock pin to IOE clock
Delay from dedicated clock pin to LE or EAB clock
Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row
Routing delay for an LE driving an IOE in the same column
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
CCIO
CCIO
CCIO
= 3.3 V ± 10% for commercial or industrial and extended use in ACEX 1K devices
= 2.5 V ± 5% for commercial or industrial and extended use in ACEX 1K devices.
= 2.5 V or 3.3 V.
Parameter
Note (1)
Altera Corporation
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
Conditions