EP3C10E144C8N Altera, EP3C10E144C8N Datasheet - Page 253

IC CYCLONE III FPGA 10K 144-EQFP

EP3C10E144C8N

Manufacturer Part Number
EP3C10E144C8N
Description
IC CYCLONE III FPGA 10K 144-EQFP
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C10E144C8N

Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
94
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-EQFP
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
94
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2427
EP3C10E144C8N

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Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Chapter Revision History
Chapter Revision History
Table 10–1. Chapter Revision History
© December 2009
December 2009
July 2009
June 2009
October 2008
July 2007
March 2007
Date
Altera Corporation
Table 10–1
Version
3.2
3.1
3.0
1.2
1.1
1.0
lists the revision history for this chapter.
Minor changes to the text.
Made minor correction to the part number.
Initial release.
Updated chapter part number.
Updated “I/O Pins Remain Tristated During Power-Up” on page 10–2.
Updated “Hot-Socketing Feature Implementation” on page 10–3.
Updated “POR Circuitry” on page 10–4.
Updated chapter to new template.
Added handnote to the “Cyclone III Hot-Socketing Specifications” section.
Updated “I/O Pins Remain Tri-stated During Power-Up” section.
Updated Figure 10–3.
Added chapter TOC and “Referenced Documents” section.
Changes Made
Cyclone III Device Handbook, Volume 1
10–5

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