AT40K10-2DQC Atmel, AT40K10-2DQC Datasheet - Page 10

• Manufacturer Part Number: AT40K10-2DQC
• Description: IC FPGA 576 CELL 208-PQFP
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K10-2DQC

• Number Of Logic Elements/cells: 576
• Total Ram Bits: 4608
• Number Of I /o: 161
• Number Of Gates: 20000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -

Figure 6. Some Single Cell Modes
10
CARRY IN
C
D
A
B
A
B
C
EN
AT40K/AT40KLV Series FPGA
C
D
C
A
B
A
B
D Q
D Q
D Q
D Q
Q (Registered)
and/or
PRODUCT
and/or
and/or
SUM
or
SUM (Registered)
CARRY
PRODUCT (Registered)
or
CARRY
and/or
CARRY
Q
Q
Q
Synthesis Mode. This mode is particularly important for
the use of VHDL/Verilog design. VHDL/Verilog Synthesis
tools generally will produce as their output large amounts
of random logic functions. Having a 4-input LUT structure
gives efficient random logic optimization without the
delays associated with larger LUT structures. The output
of any cell may be registered, tri-stated and/or fed back
into a core cell.
Arithmetic Mode is frequently used in many designs.
As can be seen in the figure, the AT40K/AT40KLV core cell
can implement a 1-bit full adder (2-input adder with both
Carry In and Carry Out) in one core cell. Note that the
sum output in this diagram is registered. This output could
then be tri-stated and/or fed back into the cell.
DSP/Multiplier Mode. This mode is used to efficiently
implement array multipliers. An array multiplier is an array
of bitwise multipliers, each implemented as a full adder
with an upstream AND gate. Using this AND gate and the
diagonal interconnects between cells, the array multiplier
structure fits very well into the AT40K/AT40KLV
architecture.
Counter Mode. Counters are fundamental to almost all
digital designs. They are the basis of state machines,
timing chains and clock dividers. A counter is essentially
an increment by one function (i.e., an adder), with the
input being an output (or a decode of an output) from the
previous stage. A 1-bit counter can be implemented in one
core cell. Again, the output can be registered, tri-stated
and/or fed back.
Tri-state/Mux Mode. This mode is used in many
telecommunications applications, where data needs to be
routed through more than one possible path. The output of
the core cell is very often tri-statable for many inputs to
many outputs data switching.
0896C–FPGA–04/02