XC4VSX35-10FFG668C Xilinx Inc, XC4VSX35-10FFG668C Datasheet - Page 29

• Manufacturer Part Number: XC4VSX35-10FFG668C
• Description: IC FPGA VIRTEX-4 35K 668-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VSX35-10FFG668C

• Total Ram Bits: 3538944
• Number Of Logic Elements/cells: 34560
• Number Of Labs/clbs: 3840
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 668-BBGA, FCBGA
• No. Of Logic Blocks: 3840
• No. Of Macrocells: 34560
• Family Type: Virtex-4
• No. Of Speed Grades: 10
• No. Of I/o's: 448
• Clock Management: DCM
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML402-UNI-G - EVALUATION PLATFORM VIRTEX-4807-1005 - DAUGHTER CARD WITH VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1498

Input Delay Switching Characteristics
Table 35: Input Delay Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
4.
IDELAYCTRL
T
F
IDELAYCTRL_REF_PRECISION
T
IDELAY
T
T
T
F
IDELAYCTRLCO_RDY
IDELAYCTRL_REF
IDELAYCTRL_RPW
IDELAYRESOLUTION
IDELAYTOTAL_ERR
IDELAYPAT_JIT
MAX
Refer to Xilinx Application Note
See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the
This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
Units in ps peak-to-peak per tap.
Symbol
(2)
XAPP707
Reset to Ready for IDELAYCTRL
(Maximum)
REFCLK frequency
REFCLK precision
Minimum Reset pulse width
IDELAY Chain Delay Resolution
Cumulative delay at a given tap
Pattern dependent period jitter in delay
chain for clock pattern
Pattern dependent period jitter in delay
chain for random data pattern (PRBS 23)
C clock maximum frequency
for details on IDELAY timing characteristics.
Description
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(3)
Virtex-4 FPGA User
10 ± 2
3.00
50.0
-12
200
±10
300
75
0
± 0.07[(tap −1) x 75 +34]
[(tap −1) x 75 +34]
Guide: Chapter 7, SelectIO Logic Resources.
Speed Grade
10 ± 2
3.00
50.0
-11
200
±10
250
75
0
10 ± 2
3.00
50.0
-10
200
±10
250
75
0
Note (4)
Note (4)
Units
MHz
MHz
MHz
µs
ns
ps
ps
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