XC3S1200E-4FGG400C Xilinx Inc, XC3S1200E-4FGG400C Datasheet - Page 213

• Manufacturer Part Number: XC3S1200E-4FGG400C
• Description: IC SPARTAN-3E FPGA 1200K 400FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S1200E-4FGG400C

• Total Ram Bits: 516096
• Number Of Logic Elements/cells: 19512
• Number Of Labs/clbs: 2168
• Number Of I /o: 304
• Number Of Gates: 1200000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 400-BGA
• No. Of Logic Blocks: 19512
• No. Of Gates: 1200000
• No. Of Macrocells: 19512
• No. Of Speed Grades: 4
• No. Of I/o's: 304
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1480

User I/Os by Bank
Table 149
pins are distributed between the four I/O banks on the
FG320 package.
Table 149: User I/Os Per Bank for XC3S500E in the FG320 Package
Table 150: User I/Os Per Bank for XC3S1200E and XC3S1600E in the FG320 Package
DS312-4 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Package
Package
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Edge
Edge
and
R
Table 150
I/O Bank
I/O Bank
0
1
2
3
0
1
2
3
indicate how the available user-I/O
Maximum
Maximum
232
250
I/O
I/O
58
58
58
58
61
63
63
63
102
120
I/O
I/O
29
22
17
34
34
25
23
38
www.xilinx.com
INPUT
INPUT
14
10
13
11
48
12
12
11
12
47
All Possible I/O Pins by Type
All Possible I/O Pins by Type
DUAL
DUAL
21
24
46
21
24
46
1
0
1
0
VREF
VREF
20
21
6
5
4
5
6
5
5
5
Pinout Descriptions
(1)
(1)
CLK
CLK
0
0
0
0
16
16
8
8
(2)
(2)
8
8
(2)
(2)
(1)
(1)
213