XC3S500E-4FGG320C Xilinx Inc, XC3S500E-4FGG320C Datasheet - Page 38

• Manufacturer Part Number: XC3S500E-4FGG320C
• Description: IC SPARTAN-3E FPGA 500K 320FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FGG320C

• Total Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Number Of I /o: 232
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 320-BGA
• No. Of Logic Blocks: 10476
• No. Of Gates: 500000
• No. Of Macrocells: 10476
• No. Of Speed Grades: 4
• No. Of I/o's: 250
• Clock Management: DLL
• Package: 320FBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 232
• Ram Bits: 368640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1526

Functional Description
Block RAM Port Signal Definitions
Representations
RAMB16_S[w
RAMB16_S[w] with their associated signals are shown in
Figure 32a
defined in
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
38
Notes:
1.
2.
3.
4.
DIA[w
DIB[w
ADDRA[r
ADDRB[r
DIPB[p
DIPA[p
w
p
r
The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
A
Table
A
A
and
and r
A
B
and p
and w
–p
–p
A
]_S[w
SSRA
A
A
A
SSRB
B
B
B
CLKA
CLKB
B
Figure
WEA
WEB
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
23. The control signals (WE, EN, CLK, and
ENA
ENB
B
B
are integers representing the address bus width at ports A and B, respectively.
are integers that indicate the number of data path lines serving as parity bits.
are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
B
of
]
32b, respectively. These signals are
and
RAMB16_S
(a) Dual-Port
the
the
dual-port
W A
single-port
_S
W B
Figure 32: Block RAM Primitives
DOPA[p
DOA[w
DOPB[p
DOB[w
primitive
primitive
A
B
A
–p
B
–p
www.xilinx.com
–1:0]
–1:0]
A
B
–1:0]
–1:0]
Design Note
Whenever a block RAM port is enabled (ENA or
ENB = High), all address transitions must meet the data
sheet setup and hold times with respect to the port clock
(CLKA or CLKB), as shown in
requirement must be met even if the RAM read output is of
no interest.
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
SSR
CLK
WE
EN
(b) Single-Port
RAMB16_Sw
DS312-2 (v3.8) August 26, 2009
Table 103, page
Product Specification
DOP[p–1:0]
DO[w–p–1:0]
DS312-2_03_111105
142.This
R