XCS20XL-4TQG144C Xilinx Inc, XCS20XL-4TQG144C Datasheet - Page 60
![IC SPARTAN-XL FPGA 20K 144-TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XCS20XL-4TQG144C
Manufacturer Part Number
XCS20XL-4TQG144C
Description
IC SPARTAN-XL FPGA 20K 144-TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-XLr
Datasheet
1.XCS05XL-4VQG100C.pdf
(83 pages)
Specifications of XCS20XL-4TQG144C
Number Of Logic Elements/cells
950
Number Of Labs/clbs
400
Total Ram Bits
12800
Number Of I /o
113
Number Of Gates
20000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1293
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCS20XL-4TQG144C
Manufacturer:
LATTTICE
Quantity:
210
Company:
Part Number:
XCS20XL-4TQG144C
Manufacturer:
XILINX
Quantity:
1 250
Part Number:
XCS20XL-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
60
Notes:
1.
2.
Setup Times
Hold Times
Propagation Delays
Delay Adder for Input with Full Delay Option
Global Set/Reset
Symbol
T
T
T
T
T
T
T
T
T
T
POCK
Delay
MRW
ECIK
PICK
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
IKRI
IKLI
PID
RRI
PLI
Clock Enable (EC) to Clock (IK)
Pad to Clock (IK), no delay
Pad to Fast Capture Latch Enable (OK), no delay
All Hold Times
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
T
T
Minimum GSR pulse width
Delay from GSR input to any Q
PICKD
PDLI
= T
= T
PLI
PICK
+ T
+ T
Delay
Delay
Description
www.xilinx.com
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
Device
10.5
Min
1.0
0.0
4.0
4.8
5.0
5.5
6.5
0.0
0.7
-
-
-
-
-
-
-
-
-
-5
Speed Grade
Max
10.0
11.0
12.0
0.9
2.1
1.0
1.1
9.0
9.5
-
-
-
-
-
-
-
-
-
-
DS060 (v1.8) June 26, 2008
11.5
Min
0.0
1.2
0.8
0.0
4.7
5.6
5.9
6.5
7.6
-
-
-
-
-
-
-
-
-
Product Specification
-4
Max
10.5
11.0
11.5
12.5
13.5
1.1
2.5
1.1
1.2
-
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R