XC3S50AN-4TQG144C Xilinx Inc, XC3S50AN-4TQG144C Datasheet - Page 90
![IC SPARTAN-3AN FPGA 50K 144TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S50AN-4TQG144C
Manufacturer Part Number
XC3S50AN-4TQG144C
Description
IC SPARTAN-3AN FPGA 50K 144TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S50AN-4TQG144C
Total Ram Bits
55296
Number Of Logic Elements/cells
1584
Number Of Labs/clbs
176
Number Of I /o
108
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
No. Of Logic Blocks
1584
No. Of Gates
50000
No. Of Macrocells
1584
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
108
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1555
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S50AN-4TQG144C
Manufacturer:
TOSHIBA
Quantity:
1 000
Company:
Part Number:
XC3S50AN-4TQG144C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S50AN-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
FTG256 Footprint (XC3S50AN)
DS557 (v4.1) April 1, 2011
Product Specification
53
20
51
2
I/O: Unrestricted,
general-purpose user I/O
INPUT: Unrestricted,
general-purpose input pin
CONFIG: Dedicated
configuration pins
N.C.: Not connected
(XC3S50AN only)
M
A
B
C
D
E
G
H
K
N
P
R
F
J
L
T
VREF_3
LHCLK1
LHCLK5
LHCLK7
L01N_3
L03P_3
L03N_3
L08P_3
L08N_3
L11N_3
L14N_3
L15N_3
L20P_3
L20N_3
L22N_3
L23P_3
GND
GND
N.C.
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
VCCO_3
VCCO_3
VCCO_3
LHCLK0
LHCLK4
L01P_3
L11P_3
L14P_3
L22P_3
L23N_3
L02P_2
L02N_2
CSO_B
GND
GND
TMS
N.C.
N.C.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M2
2
RDWR_B
LHCLK2
LHCLK3
LHCLK6
L19P_0
L19N_0
L02N_3
L12P_3
L12N_3
L15P_3
L24P_3
L03P_2
L04P_2
TRDY2
IRDY2
GND
GND
N.C.
N.C.
N.C.
N.C.
N.C.
VS2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(Differential Outputs)
3
Figure 20: XC3S50AN FTG256 Package Footprint (Top View)
25
30
28
VCCO_2
(Differential Outputs)
VREF_0
INPUT
INPUT
VREF_3
L18P_0
L18N_0
L20P_0
L02P_3
L04P_3
L04N_3
L24N_3
L01P_2
L01N_2
L05P_2
4
N.C.
N.C.
N.C.
N.C.
N.C.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1
M0
4
DUAL: Configuration pins,
then possible user I/O
CLK: User I/O, input, or
global buffer input
JTAG: Dedicated JTAG
port pins
GND: Ground
PUDC_B
VCCAUX
VCCO_0
VCCO_3
INPUT
INPUT
INPUT
VREF_2
L17P_0
L17N_0
L20N_0
L21P_3
L25P_3
L04N_2
L06P_2
L05N_2
GND
GND
N.C.
N.C.
VS0
I/O
I/O
I/O
I/O
I/O
I/O
D7
5
VCCAUX
INPUT
INPUT
INPUT
INPUT
VREF_3
L15P_0
L15N_0
L16N_0
L21N_3
L25N_3
L03N_2
L06N_2
GND
GND
N.C.
N.C.
N.C.
N.C.
VS1
I/O
I/O
I/O
I/O
I/O
D6
6
VCCINT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF_2
L16P_0
L13P_3
L13N_3
L08P_2
GND
GND
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
I/O
I/O
D5
7
www.xilinx.com
Bank 2
VCCINT
VCCINT
GCLK10
GCLK11
VCCO_0
GCLK14
VCCO_2
GCLK15
INPUT
INPUT
VREF_2
L12P_0
L12N_0
L11P_0
L11N_0
L08N_2
L10P_2
L10N_2
GCLK8
GCLK9
GND
GND
N.C.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D4
8
Bank 0
15
16
VCCINT
VCCINT
VCCO_0
VREF_0
VREF_2
VCCO_2
INPUT
INPUT
INPUT
6
4
L10N_0
L10P_0
L09N_0
L11P_2
L11N_2
L12P_2
L12N_2
GCLK7
GCLK6
GCLK5
GCLK0
GCLK1
GCLK2
GCLK3
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
VREF: User I/O or input
voltage reference for bank
VCCO: Output voltage
supply for bank
VCCINT: Internal core
supply voltage (+1.2V)
VCCAUX: Auxiliary supply
voltage
VCCINT
VREF_2
INPUT
INPUT
INPUT
L08N_0
L08P_0
L09P_0
L13P_1
L14P_2
L14N_2
GCLK4
CSI_B
GND
GND
N.C.
N.C.
N.C.
N.C.
N.C.
MOSI
10
I/O
I/O
I/O
I/O
I/O
Spartan-3AN FPGA Family: Pinout Descriptions
(Differential Outputs)
(Differential Outputs)
VCCAUX
VREF_2
INPUT
INPUT
INPUT
INPUT
INPUT
AWAKE
L07N_0
L07P_0
L03N_0
L25N_1
L21N_1
L13N_1
L04P_1
L16N_2
L16P_2
L15N_2
L15P_2
DOUT
GND
GND
N.C.
11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_1
VCCAUX
VCCO_2
VREF_1
VREF_1
VREF_1
INPUT
INPUT
INPUT
INPUT
INPUT
L03P_0
L25P_1
L21P_1
L10P_1
L04N_1
L17N_2
L17P_2
INIT_B
GND
GND
N.C.
N.C.
12
I/O
I/O
I/O
I/O
D3
VCCO_0
L20P_2
L04N_0
L01N_0
L01P_0
L23P_1
L20N_1
L10N_1
L01P_1
L18P_2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
HDC
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D1
D2
DIN/MISO
2
RHCLK5
RHCLK4
RHCLK1
L02N_0
L23N_1
L14N_1
L11N_1
L01N_1
L20N_2
L18N_2
L04P_0
L20P_1
L14P_1
GND
GND
CCLK
N.C.
N.C.
N.C.
N.C.
LDC2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
14
D0
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
VCCO_1
RHCLK6
VCCO_1
RHCLK0
VCCO_1
VREF_0
L24N_1
L22N_1
L02N_1
DONE
L02P_0
L15P_1
L11P_1
L02P_1
IRDY1
GND
GND
TCK
N.C.
N.C.
LDC0
LDC1
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS529-4_09_012009
RHCLK7
RHCLK3
RHCLK2
L15N_1
L12N_1
L03N_1
L24P_1
L22P_1
TRDY1
L12P_1
L03P_1
GND
TDO
GND
N.C.
N.C.
N.C.
N.C.
N.C.
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
90