EP1S20F780C5 Altera, EP1S20F780C5 Datasheet - Page 227
EP1S20F780C5
Manufacturer Part Number
EP1S20F780C5
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F780C5
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1114
Available stocks
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Quantity
Price
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Altera Corporation
January 2006
Definition of I/O Skew
I/O skew is defined as the absolute value of the worst-case difference in
clock-to-out times (t
common clock source.
I/O bank skew is made up of the following components:
■
■
Figure 4–5
bank, being fed by a common clock source. The clock can come from an
input pin or from a PLL output.
Figure 4–5. I/O Skew within an I/O Bank
Clock network skews: This is the difference between the arrival times
of the clock at the clock input port of the two IOE registers.
Package skews: This is the package trace length differences between
(I/O pad A to I/O pin A) and (I/O pad B to I/O pin B).
Slow Edge
Common Source of GCLK
shows an example of two IOE registers located in the same
I/O Pin B
Fast Edge
I/O Pin A
I/O Skew
CO
I/O Bank
) between any two output registers fed by a
I/O Skew
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
I/O Pin A
I/O Pin B
4–57
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