EP2S30F484C3N Altera, EP2S30F484C3N Datasheet - Page 180

• Manufacturer Part Number: EP2S30F484C3N
• Description: IC STRATIX II FPGA 30K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S30F484C3N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• No. Of Macrocells: 33880
• Family Type: Stratix II
• No. Of I/o's: 342
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.6V
• Operating Frequency Max: 550MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1890; EP2S30F484C3N

Timing Model
5–44
Stratix II Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
Table 5–50. EP2S30 Row Pins Regional Clock Timing Parameters
Table 5–51. EP2S30 Row Pins Global Clock Timing Parameters
Table 5–52. EP2S60 Column Pins Regional Clock Timing Parameters
Parameter
Parameter
Parameter
Industrial
Industrial
Industrial
-0.135
-0.135
-0.091
1.304
1.309
1.289
1.294
1.681
1.524
0.066
-0.13
-0.14
Minimum Timing
Minimum Timing
Minimum Timing
EP2S60 Clock Timing Parameters
Tables 5–52
for EP2S60 devices.
Commercial
Commercial
Commercial
–0.158
–0.153
-0.154
-0.149
-0.101
1.184
1.189
1.352
1.357
1.762
1.597
0.064
through
5–55
-3 Speed
-3 Speed
-3 Speed
–0.208
–0.212
Grade
Grade
-0.169
-0.173
Grade
1.966
1.962
2.238
2.234
show the maximum clock timing parameters
2.945
2.703
0.279
0.037
-4 Speed
-4 Speed
-4 Speed
–0.254
–0.258
Grade
Grade
-0.205
-0.209
Grade
2.251
2.247
2.567
2.563
3.381
3.103
0.311
0.033
-5 Speed
-5 Speed
-5 Speed
Altera Corporation
–0.302
–0.307
Grade
Grade
-0.254
-0.259
Grade
2.616
2.611
2.990
2.985
3.931
3.607
0.348
0.024
April 2011
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns