EP1S20F780C7N Altera, EP1S20F780C7N Datasheet - Page 63

IC STRATIX FPGA 20K LE 780-FBGA

EP1S20F780C7N

Manufacturer Part Number
EP1S20F780C7N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F780C7N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1855
EP1S20F780C7N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F780C7N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S20F780C7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S20F780C7N
Manufacturer:
ALTERA
0
Part Number:
EP1S20F780C7N
Manufacturer:
ALTERA
Quantity:
200
Part Number:
EP1S20F780C7N
0
Altera Corporation
July 2005
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dual-
port memory. You can use up to two clocks in this mode. The write clock
controls the block’s data inputs, wraddress, and wren. The read clock
controls the data output, rdaddress, and rden. The memory blocks
support independent clock enables for each clock and asynchronous clear
signals for the read- and write-side registers.
memory block in read/write clock mode.
Stratix Device Handbook, Volume 1
Figure 2–27
Stratix Architecture
shows a
2–49

Related parts for EP1S20F780C7N