EP2C50F484C6 Altera, EP2C50F484C6 Datasheet - Page 70

• Manufacturer Part Number: EP2C50F484C6
• Description: IC CYCLONE II FPGA 50K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C50F484C6

• Number Of Logic Elements/cells: 50528
• Number Of Labs/clbs: 3158
• Total Ram Bits: 594432
• Number Of I /o: 294
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2116

I/O Structure & Features
Figure 2–28. EP2C5 & EP2C8 I/O Banks
Notes to
(1)
(2)
(3)
(4)
(5)
2–58
Cyclone II Device Handbook, Volume 1
3.3-V PCI & PCI-X
Also Supports the
I/O Standards
This is a top view of the silicon die.
This is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.
I/O Bank 1
Figure
I/O Bank 1
2–28:
All I/O Banks Support
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■
■
■
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Notes
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
LVDS
RSDS
mini-LVDS
LVPECL (3)
SSTL-2 Class I and II
SSTL-18 Class I
HSTL-18 Class I
HSTL-15 Class I
Differential SSTL-2 (4)
Differential SSTL-18 (4)
Differential HSTL-18 (5)
Differential HSTL-15 (5)
I/O Bank 2
I/O Bank 4
(1),
(2)
HSTL-18 Class II, & HSTL-15
HSTL-18 Class II, & HSTL-15
I/O Bank 2 Also Supports
I/O Bank 4 Also Supports
Class II I/O Standards
Class II I/O Standards
the SSTL-18 Class II,
the SSTL-18 Class II,
Power Bus
Individual
I/O Bank 3
Altera Corporation
I/O Bank 3
Also Supports the
3.3-V PCI & PCI-X
I/O Standards
February 2007