EP2C35F484C7 Altera, EP2C35F484C7 Datasheet - Page 42

• Manufacturer Part Number: EP2C35F484C7
• Description: IC CYCLONE II FPGA 33K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C35F484C7

• Number Of Logic Elements/cells: 33216
• Number Of Labs/clbs: 2076
• Total Ram Bits: 483840
• Number Of I /o: 322
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 33216
• # I/os (max): 322
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33216
• Ram Bits: 483840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1077; EP2C35F484C7ES

Embedded Memory
2–30
Cyclone II Device Handbook, Volume 1
Memory Modes
Table 2–7
M4K memory blocks.
1
Single-port memory
Simple dual-port memory
Simple dual-port with mixed
width
True dual-port memory
True dual-port with mixed
width
Embedded shift register
ROM
FIFO buffers
Table 2–7. M4K Memory Modes
Memory Mode
Embedded Memory can be inferred in your HDL code or
directly instantiated in the Quartus II software using the
MegaWizard
summarizes the different memory modes supported by the
®
Plug-in Manager Memory Compiler feature.
M4K blocks support single-port mode, used when
simultaneous reads and writes are not required.
Single-port memory supports non-simultaneous
reads and writes.
Simple dual-port memory supports a
simultaneous read and write.
Simple dual-port memory mode with different
read and write port widths.
True dual-port mode supports any combination of
two-port operations: two reads, two writes, or one
read and one write at two different clock
frequencies.
True dual-port mode with different read and write
port widths.
M4K memory blocks are used to implement shift
registers. Data is written into each address
location at the falling edge of the clock and read
from the address at the rising edge of the clock.
The M4K memory blocks support ROM mode. A
MIF initializes the ROM contents of these blocks.
A single clock or dual clock FIFO may be
implemented in the M4K blocks. Simultaneous
read and write from an empty FIFO buffer is not
supported.
Description
Altera Corporation
February 2007