EP2C35U484I8N Altera, EP2C35U484I8N Datasheet - Page 75

• Manufacturer Part Number: EP2C35U484I8N
• Description: IC CYCLONE II FPGA 33K 484-UBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C35U484I8N

• Number Of Logic Elements/cells: 33216
• Number Of Labs/clbs: 2076
• Total Ram Bits: 483840
• Number Of I /o: 322
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-UBGA
• For Use With: P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2115

IEEE Std. 1149.1
(JTAG) Boundary
Scan Support
Altera Corporation
February 2007
CII51003-2.2
f
All Cyclone
the IEEE Std. 1149.1. JTAG boundary-scan testing can be performed
either before or after, but not during configuration. Cyclone II devices can
also use the JTAG port for configuration with the Quartus
hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
Cyclone II devices support IOE I/O standard reconfiguration through the
JTAG BST chain. The JTAG chain can update the I/O standard for all
input and output pins any time before or during user mode through the
CONFIG_IO instruction. You can use this capability for JTAG testing
before configuration when some of the Cyclone II pins drive or receive
from other devices on the board using voltage-referenced standards.
Since the Cyclone II device might not be configured before JTAG testing,
the I/O pins may not be configured for appropriate electrical standards
for chip-to-chip communication. Programming the I/O standards via
JTAG allows you to fully test I/O connections to other devices.
For information on I/O reconfiguration, refer to the MorphIO: An I/O
Reconfiguration Solution for Altera Devices White Paper.
A device operating in JTAG mode uses four required pins: TDI, TDO, TMS,
and TCK. The TCK pin has an internal weak pull-down resister, while the
TDI and TMS pins have weak internal pull-up resistors. The TDO output
pin and all JTAG input pin voltage is determined by the V
where it resides. The bank V
1.8-, 2.5-, or 3.3-V compatible.
1
Stratix
within the first 8 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II, Stratix,
Cyclone II or Cyclone devices are in the 9th of further position,
they fail configuration. This does not affect Signal Tap II.
®
II devices provide JTAG BST circuitry that complies with
®
II, Stratix, Cyclone II and Cyclone devices must be
3. Configuration & Testing
CCIO
selects whether the JTAG inputs are 1.5-,
CCIO
®
II software or
of the bank
3–1