EP2C20F484I8N Altera, EP2C20F484I8N Datasheet - Page 89

• Manufacturer Part Number: EP2C20F484I8N
• Description: IC CYCLONE II FPGA 20K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C20F484I8N

• Number Of Logic Elements/cells: 18752
• Number Of Labs/clbs: 1172
• Total Ram Bits: 239616
• Number Of I /o: 315
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 18752
• # I/os (max): 315
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 18752
• Ram Bits: 239616
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• For Use With: P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2105

Conclusion
Document
Revision History
Altera Corporation
February 2007
February 2007
v3.1
July 2005 v2.0
February 2005
v1.1
June 2004 v1.0
Table 4–1. Document Revision History
Document
Version
Date &
●
●
●
●
Updated technical content throughout.
Removed ESD section.
Added document to the Cyclone II Device Handbook.
Added document revision history.
Updated
section.
Updated
Added footnote to
If you cannot meet the maximum V
use an external component to hold nCONFIG low until the power supplies
have reached their minimum recommend operating levels. Otherwise,
the device may not properly configure and enter user mode.
Cyclone II devices are hot socketable and support all power-up and
power-down sequences with the one requirement that V
be powered up and down within 100 ms of each other to keep the I/O
pins from driving out. Cyclone II devices do not require any external
devices for hot socketing and power sequencing.
Table 4–1
“I/O Pins Remain Tri-Stated during Power-Up”
“Power-On Reset Circuitry”
Figure
Changes Made
shows the revision history for this document.
4–3.
section.
CC
Cyclone II Device Handbook, Volume 1
ramp time requirement, you must
Hot Socketing & Power-On Reset
●
●
●
Specified V
supplies must be GND
when "not powered".
Added clarification about
input-tristate behavior.
Added infomation on V
monotonic ramp.
Summary of Changes
CCIO
CCIO
and V
and V
CCINT
CCINT
CC
4–7