EP1K50QC208-1 Altera, EP1K50QC208-1 Datasheet - Page 83

IC ACEX 1K FPGA 50K 208-PQFP

EP1K50QC208-1

Manufacturer Part Number
EP1K50QC208-1
Description
IC ACEX 1K FPGA 50K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K50QC208-1

Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
147
Number Of Gates
199000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1007

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Figure 31. ACEX 1K I
Configuration &
Operation
EP1K30
I
Current (mA)
CC
Supply
100
80
60
40
20
0
CCACTIVE
The ACEX 1K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The ACEX 1K architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as V
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The ACEX 1K POR time does not exceed 50 s.
1
vs. Operating Frequency
EP1K100
I
Current (mA)
Frequency (MHz)
CC
Supply
50
When configuring with a configuration device, refer to the
relevant configuration device data sheet for POR timing
information.
300
200
100
0
100
ACEX 1K Programmable Logic Device Family Data Sheet
Frequency (MHz)
EP1K50
I
Current (mA)
CC
Supply
50
200
150
100
50
CC
0
100
rises, the device initiates a
Frequency (MHz)
50
100
83
13

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