EPF6016ATC144-3 Altera, EPF6016ATC144-3 Datasheet - Page 12
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EPF6016ATC144-3
Manufacturer Part Number
EPF6016ATC144-3
Description
IC FLEX 6000 FPGA 16K 144-TQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet
1.EPF6010ATC100-3N.pdf
(52 pages)
Specifications of EPF6016ATC144-3
Number Of Logic Elements/cells
1320
Number Of Labs/clbs
132
Number Of I /o
117
Number Of Gates
16000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Family Name
FLEX 6000
Number Of Usable Gates
16000
Number Of Logic Blocks/elements
1320
# Registers
1320
# I/os (max)
117
Frequency (max)
142.86MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
3.3V
Logic Cells
1320
Device System Gates
16000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1276
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF6016ATC144-3
Manufacturer:
ALTERA
Quantity:
12 388
Part Number:
EPF6016ATC144-3
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPF6016ATC144-3N
Manufacturer:
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Quantity:
3 000
Company:
Part Number:
EPF6016ATC144-3N
Manufacturer:
ALTERA
Quantity:
1 078
Part Number:
EPF6016ATC144-3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
FLEX 6000 Programmable Logic Device Family Data Sheet
12
Cascade Chain
The cascade chain enables the FLEX 6000 architecture to implement very
wide fan-in functions. Adjacent LUTs can be used to implement portions
of the function in parallel; the cascade chain serially connects the
intermediate values. The cascade chain can use a logical AND or logical
OR gate (via De Morgan’s inversion) to connect the outputs of adjacent
LEs. Each additional LE provides four more inputs to the effective width
of a function, with a delay as low as 0.5 ns per LE. Cascade chain logic can
be created automatically by the Altera software during design processing,
or manually by the designer during design entry. Parameterized functions
such as LPM and DesignWare functions automatically take advantage of
cascade chains for the appropriate functions.
A cascade chain implementing an AND gate can use the register in the last
LE; a cascade chain implementing an OR gate cannot use this register
because of the inversion required to implement the OR gate.
Because the first LE of an LAB can generate control signals for that LAB,
the first LE in each LAB is not included in cascade chains. Moreover,
cascade chains longer than nine bits are automatically implemented by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from an even-numbered LAB to another even-numbered
LAB, or from an odd-numbered LAB to another odd-numbered LAB. For
example, the last LE of the first LAB in a row cascades to the second LE of
the third LAB. The cascade chain does not cross the center of the row. For
example, in an EPF6016 device, the cascade chain stops at the 11th LAB in
a row and a new cascade chain begins at the 12th LAB.
Figure 6
functions with a wide fan-in. In this example, functions of 4n variables are
implemented with n LEs. The cascade chain requires 3.4 ns to decode a
16-bit address.
shows how the cascade function can connect adjacent LEs to form
Altera Corporation