EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 74

IC CYCLONE III FPGA 5K 256-FBGA

EP3C5F256C8N

Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C5F256C8N

Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N

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0
2–30
Table 2–39. Glossary (Part 5 of 5)
Cyclone III Device Handbook, Volume 2
Letter
W
V
X
Y
Z
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C M( DC)
DIF( AC )
DIF( DC)
IC M
ID
IH
IH(A C)
IH(DC )
IL
IL ( AC )
IL ( DC)
IN
OC M
OD
OH
OL
OS
OX ( AC)
REF
REF (A C)
REF (DC )
S WING (A C)
S WING (DC )
TT
X ( AC)
Term
DC common mode input voltage.
AC differential Input Voltage—The minimum AC input differential voltage required for
switching.
DC differential Input Voltage—The minimum DC input differential voltage required for
switching.
Input Common Mode Voltage—The common mode of the differential signal at the receiver.
Input differential Voltage Swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
Voltage Input High—The minimum positive voltage applied to the input that is accepted by
the device as a logic high.
High-level AC input voltage.
High-level DC input voltage.
Voltage Input Low—The maximum positive voltage applied to the input that is accepted by
the device as a logic low.
Low-level AC input voltage.
Low-level DC input voltage.
DC input voltage.
Output Common Mode Voltage—The common mode of the differential signal at the
transmitter.
Output differential Voltage Swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter. V
Voltage Output High—The maximum positive voltage from an output that the device
considers will be accepted as the minimum positive high level.
Voltage Output Low—The maximum positive voltage from an output that the device considers
will be accepted as the maximum positive low level.
Output offset voltage—V
AC differential Output cross point voltage—The voltage at which the differential output signals
must cross.
Reference voltage for the SSTL and HSTL I/O standards.
AC input reference voltage for the SSTL and HSTL I/O standards. V
peak-to-peak AC noise on V
DC input reference voltage for the SSTL and HSTL I/O standards.
AC differential Input Voltage—AC Input differential voltage required for switching. Refer to
Input Waveforms for the SSTL Differential I/O Standard.
DC differential Input Voltage—DC Input differential voltage required for switching. Refer to
Input Waveforms for the SSTL Differential I/O Standard.
Termination voltage for the SSTL and HSTL I/O standards.
AC differential Input cross point Voltage—The voltage at which the differential input signals
must cross.
OS
= (V
REF
must not exceed 2% of V
OH
+ V
OL
) / 2.
Definitions
REF (DC)
Chapter 2: Cyclone III LS Device Data Sheet
.
© December 2009 Altera Corporation
REF (AC )
= V
REF (DC)
OD
= V
+ noise. The
OH
– V
Glossary
OL
.

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