DSP56301AG80 Freescale Semiconductor, DSP56301AG80 Datasheet

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... DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.0–3.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling wireless, telecommunications, and multimedia products. © Freescale Semiconductor, Inc., 1996, 2006. All rights reserved. 3 Memory Expansion Area ...

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... Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol PIN PIN PIN PIN Note: Values for , , , and Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications DSP56301 Technical Data, Rev. 10 pin is active when RESET Voltage Freescale Semiconductor ...

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... Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable: Program RAM Instruction Cache Size 4096 × 24 bits 3072 × 24 bits 2048 × 24 bits 1024 × 24 bits Freescale Semiconductor X Data RAM Size Y Data RAM Size Size 2048 × 24 bits 0 1024 × 24-bit 2048 × 24 bits 3072 × 24 bits 0 1024 × ...

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... DSP56301 and are necessary to design properly with the part. Documentation is available from the following sources. (See the back cover for detailed information.) • A local Freescale distributor • A Freescale semiconductor sales office • A Freescale Literature Distribution Center • The World Wide Web (WWW) ...

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... Each device also includes several no connect (NC) pins. The number of NC connections is package-dependent: the TQFP has 9 NCs and the MAP-BGA has 20 NCs. Do not connect any line, component, trace, or via to these pins. See Chapter 3 for details. Freescale Semiconductor Functional Signal Groupings DSP56301 Package Type ...

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... SRD0 PC4 STD0 PC5 Port D GPIO PD[0-2] SC[10-12] SCK1 PD3 PD4 SRD1 STD1 PD5 Port E GPIO PE0 RXD TXD PE1 PE2 SCLK Timer GPIO TIO0 TIO1 TIO2 TCK TDI TDO TMS TRST DE and GND ) and 36 GND pins that P P1 Freescale Semiconductor ...

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... Host Interface (HI32)/ Port B Signals Note: HPxx is a reference only and is not a signal name. GPIO references formerly designated as HIOxx have been renamed PBxx for consistency with other Freescale DSPs. Figure 1-2. Freescale Semiconductor PCI Bus Universal Bus HAD0 HA3 HAD1 HA4 ...

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... The user must provide adequate external decoupling capacitors. 1-4 Table 1-2. Power Inputs Description power rail. CC inputs except V CC are labeled V . CCP CC Table 1-3. Grounds Description by a 0.47 μF capacitor located as close as possible to the chip package. P DSP56301 Technical Data, Rev each other internally. On CCP Freescale Semiconductor ...

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... Output Chip-driven 1.4 Phase Lock Loop (PLL) Signal Name Type CLKOUT Output Chip-driven PCAP Input Input Freescale Semiconductor Table 1-3. Grounds Description and GND P Table 1-4. Clock Signals State During Reset External Clock/Crystal Input Interfaces the internal crystal oscillator input to an external crystal or an external clock ...

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... When the DSP is the bus master, D[0–23] provide the bidirectional data bus for external program and data memory accesses. Otherwise, D[0–23] are tri- stated. DSP56301 Technical Data, Rev. 10 Signal Description , , , , , AA3/RAS3 CAS BCLK Signal Description Signal Description Freescale Semiconductor , and ...

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... BR Output Output (deasserted) BG Input Ignored Input Freescale Semiconductor Table 1-8. External Bus Control Signals State During Reset Address Attribute or Row Address Strobe As AA, these signals function as chip selects or additional address lines. Unlike address lines, however, the AA lines do not hold their state after a read or write operation ...

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... When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. Bus Clock Not When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... Input IRQB Input MODC Input Input IRQC Input Freescale Semiconductor Table 1-9. Interrupt and Mode Control State During Reset Mode Select A Selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQA during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted ...

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... When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after power-up. This input tolerant. Host Port Usage Considerations Description DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... Input or Output HC[0–3]/ Input/Output Tri-stated HBE[0–3] HA[0–2] Input PB[16–19] Input or Output Freescale Semiconductor Host Port Usage Considerations (Continued) Description User’s Manual for details on HI32 configuration registers. DSP56301 Table 1-11. Host Interface State During Reset Host Address/Data 0–7 When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 0– ...

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... When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Bus Strobe Schmitt-trigger signal. Port B 23 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... Input Input HAEN Input HREQ Output Tri-stated HTA Output Freescale Semiconductor Table 1-11. Host Interface (Continued) State During Reset Host Parity When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Parity signal. Host DMA Acknowledge ...

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... When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this signal must be connected to a pull-up resistor or directly Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... Input HINTA Output, open Tri-stated drain PVCL Input Input Freescale Semiconductor Table 1-11. Host Interface (Continued) State During Reset Host Clock When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Bus Clock input. Non-PCI bus ...

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... Port C 2 The default configuration following reset is GPIO. For PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0. This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... Input or Output STD0 Input/Output Input PC5 Input or Output Freescale Semiconductor Enhanced Synchronous Serial Interface 0 (ESSI0) State During Reset Serial Clock Provides the serial bit rate clock for the ESSI interface for both the transmitter and receiver in Synchronous modes, or the transmitter only in Asynchronous modes ...

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... The ESSI needs at least three DSP phases inside each half of the serial clock. Port D 3 The default configuration following reset is GPIO. For PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1. This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... PE0 Input or Output TXD Output Input PE1 Input or Output Freescale Semiconductor State During Reset Serial Receive Data Receives serial data and transfers it to the ESSI receive shift register. SRD1 is an input when data is being received. Port D 4 The default configuration following reset is GPIO. For PD4, signal direction is controlled through PRR1 ...

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... Watchdog, Timer, or Pulse Modulation mode, TIO2 is output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 2 Control/Status Register (TCSR2). This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description Signal Description Freescale Semiconductor ...

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... TMS Input Input TRST Input Input DE Input/Output Input Freescale Semiconductor Table 1-16. JTAG/OnCE Interface State During Reset Test Clock A test clock signal for synchronizing JTAG test logic. This input tolerant. Test Data Input A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor ...

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... Signals/Connections 1-22 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... Therefore, a “maximum” value for a specification never occurs in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Freescale Semiconductor CAUTION DSP56301 Technical Data, Rev ...

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... GND – 0 0.3 CC GND – –40 to +100 –55 to +150 3 4 TQFP PBGA PBGA Value Value Value 49.5 48.4 25.2 7.2 9 — 4.7 5 — 6 Typ Max 3.3 3.6 Freescale Semiconductor Unit ° C ° C Unit ° C/W ° C/W ° C/W Unit V ...

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... Periodically sampled and not 100 percent tested. = 3.3 V ± 0 –40°C to +100 ° This characteristic does not apply to XTAL and PCAP. 8. Driving EXTAL to the low V power consumption, the minimum V 0.9 × V and the maximum V CC Freescale Semiconductor DC Electrical Characteristics Symbol Min V 2 2.0 IHP 0.8 × IHX CC V – ...

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... PDF × DF/MF × 0.53 × ET — PDF × DF/MF — ET — C × 0.51 × ET — PDF × DF/MF × 0.53 × ET — PDF × DF/MF × — ET — C PDF × DF/MF 2 × ET — — — C Freescale Semiconductor × × × × ...

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... EXTAL EXTAL ILX 2 5 CLKOUT with PLL disabled CLKOUT with PLL enabled 6a Freescale Semiconductor Suggested Component Values MHz OSC R = 680 kΩ ± 10% Note: Make sure that ± 20% the PCTL Register: • XTLD (bit 16 Calculations were done for a 4/20 MHz crystal • ...

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... MHz Min Max 30 200 (MF × 580) − 100 (MF × 780) − 140 MF × 830 MF × 1470 ). The recommended value in pF for C CCP Freescale Semiconductor Max 100.0 MHz ∞ 157.0 μs ∞ 157.0 μs ∞ 273.1 μs 11.0 ns 1.8 ns 1.8 ns ∞ ...

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... Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for 1 level sensitive fast interrupts 20 Delay from RD assertion to interrupt request deassertion 1 for level sensitive fast interrupts Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Expression 3 — 50 × 1000 × 75000 × ...

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... C 68.8 — 55.0 — — 150.0 — 120.0 — 100.0 — 80.0 — 100.0 — 80.0 — 150.0 — 120.0 Freescale Semiconductor Unit ...

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... V ± 0 –40°C to +100° number of wait states (measured in clock cycles, number Use the expression to compute a maximum value. RESET All Pins A[0–23] Freescale Semiconductor Expression 6 × × × × 4.25 × 2 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is ...

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... IRQA, IRQB, IRQC, IRQD, NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI 2- Figure 2-4. Synchronous Reset Timing First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General-Purpose I/O Figure 2-5. External Fast Interrupt Timing DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... IRQC, IRQD, NMI Figure 2-6. CLKOUT IRQA, IRQB, IRQC, IRQD, NMI A[0–23] Figure 2-7. RESET MODA, MODB, MODC, MODD, PINIT Freescale Semiconductor 15 16 External Interrupt Timing (Negative Edge-Triggered) 22 Synchronous Interrupt from Wait State Timing Figure 2-8. Operating Mode Select Timing DSP56301 Technical Data, Rev ...

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... Recovery from Stop State Using IRQA 26 25 Recovery from Stop State Using IRQA Interrupt Service DMA Source Address 29 First Interrupt Instruction Execution External Memory Access (DMA Source) Timing DSP56301 Technical Data, Rev. 10 First Instruction Fetch First IRQA Interrupt Instruction Fetch Freescale Semiconductor ...

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... WR assertion to data active 111 WR deassertion to data high impedance 112 Previous RD deassertion to data active (write) 113 RD deassertion time 114 WR deassertion time Freescale Semiconductor SRAM Read and Write Accesses 1 Expression ( × T − 4.0 [1 ≤ WS ≤ ( × T − 4.0 [4 ≤ WS ≤ ( × T − 4.0 [WS ≥ 0.25 × ...

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... MHz 100 MHz Unit Min Max Min Max 2.3 — 1.0 — ns 11.6 — 8.5 — ns 1.1 — 0.5 — ns 13.6 — 10.5 — ns 26.1 — 20.5 — ns 5.1 — 4.5 — — 0 — ns 117 106 118 119 Data In Freescale Semiconductor ...

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... A[0–23] AA[0– D[0–23] Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Freescale Semiconductor 100 107 101 102 114 108 Figure 2-13. SRAM Write Access DSP56301 Technical Data, Rev ...

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... Note: This figure should be used for primary selection. For exact and detailed timings see the following tables. 120 66 80 100 3 Wait states 4 Wait states DRAM Page Mode Wait States Selection Guide DSP56301 Technical Data, Rev. 10 Chip frequency (MHz) Freescale Semiconductor ...

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... RD deassertion always occurs after CAS deassertion; therefore, the restricted timing this time, there are no DRAMs fast enough to fit with two wait states Page mode @ 100MHz (see Table 2-14). However, DRAM speeds are approaching two-wait-state compatibility. Freescale Semiconductor DRAM Page Mode Timings, Two Wait States Symbol t ...

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... C − 4.3 11.3 — 8.2 — C − 4.0 39.8 — 31.0 — C − 5.7 — 25.6 — 19.3 C 0.0 — 0.0 — – 1.5 7.9 — 6.0 — C — 3.1 — 2.5 C equals 4 × PC and not t . OFF GZ Freescale Semiconductor Unit ...

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... BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. N/A = does not apply because 100 MHz requires a minimum of three wait states deassertion always occurs after CAS deassertion; therefore, the restricted timing is t Freescale Semiconductor DRAM Page Mode Timings, Four Wait States Symbol Expression 5 × ...

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... Address 143 132 133 153 154 Data In Data In DRAM Page Mode Read Accesses DSP56301 Technical Data, Rev. 10 136 135 138 142 Last Column Address 147 148 156 Data Out 136 135 138 142 Last Column Address 152 134 Data In Freescale Semiconductor ...

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... RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion Freescale Semiconductor Note: This figure should be used for primary selection. For exact and detailed timings, see the following tables. 120 40 66 ...

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... C 1.5 × T − 4.0 14.8 — 1.75 × T − 4.0 17.9 — 8.5 × T − 4.0 102.3 — 7.5 × T − 6.5 — 87 0.0 — ns 0.75 × T − 1.5 7.9 — 0.25 × T — 3 and not t . OFF GZ Freescale Semiconductor ...

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... RAS assertion to WR deassertion 182 WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) Freescale Semiconductor 3 Symbol Expression 12 × MHz: RAC 6.25 × T 100 MHz: 6.25 × ...

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... C − 4.0 74.1 — 58.5 — C − 4.0 99.1 — 78.5 — C − 4.0 55.4 — 43.5 — C ± 2 41.8 45.8 33.0 37.0 C ± 2.0 32.4 36.4 25.5 29.5 C − 4.0 92.9 — 73.5 — C Freescale Semiconductor Unit Unit ...

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... The number of wait states for an out-of-page access is specified in the DCR. 2. The refresh period is specified in the DCR deassertion always occurs after CAS deassertion; therefore, the restricted timing Either must be satisfied for read cycles. RCH RRH Freescale Semiconductor 3 Symbol Expression 6.25 × 6.25 × ASR 2.75 × T ...

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... Row Address Column Address 172 177 191 160 159 158 192 DRAM Out-of-Page Read Access DSP56301 Technical Data, Rev. 10 157 162 164 174 176 179 178 193 161 Data In Freescale Semiconductor ...

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... RAS CAS A[0–23 D[0–23] Figure 2-19. RAS CAS WR Freescale Semiconductor 162 163 165 167 169 168 170 173 171 172 Row Address 181 188 182 184 183 187 185 194 DRAM Out-of-Page Write Access 157 162 163 190 170 ...

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... Freescale Semiconductor ...

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... D[0–23] 208 RD D[0–23] Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-22. Freescale Semiconductor 198 210 203 Data Out 208 202 206 Synchronous Bus Timings 1 WS (BCR Controlled) ...

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... Freescale Semiconductor ...

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... Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-24. Bus Release Timings Case 1 (BRT Bit in Operating Mode Register Cleared) Freescale Semiconductor 212 213 215 Figure 2-23. ...

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... In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on the same bus in the non-overlap manner shown in Figure 2-26. 2-32 214 213 221 223 Asynchronous Bus Arbitration Timing Expression 4 2.5 × × DSP56301 Technical Data, Rev. 10 219 218 224 1 MHz 100 MHz Unit Min Max Min Max — 25 — — 25 — ns Freescale Semiconductor ...

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... HBS Deassertion to Data Strobe Deassertion 311 Data Out Valid to TA Assertion (HBS Not Used—Tied to V 312 Data Out Active from Read Data Strobe Assertion Freescale Semiconductor 250 250+251 Asynchronous Bus Arbitration Timing inputs and synchronization circuits for some time after ...

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... C 5.8 — 4.6 — 0.0 — 0.0 — 2.5 — 2.0 — — 22.2 — 19.6 2.5 — 2.0 — — 22.2 — 19.6 2.5 — 2.0 — — 22.2 — 19.6 2.5 — 2.0 — Freescale Semiconductor Unit ...

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... Data Strobe Deasserted Hold from HIRQ Deassertion 1 (HIRH = 0) 328 HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1) 329 HIRQ Deassertion from Data Strobe Assertion 1 (HIRH = 1, HIRD = 1) Freescale Semiconductor Universal Bus Mode Timing Parameters (Continued) Expression 3 2 Universal Bus Mode, Synchronous Port A Type Host Timing Expression 3 × ...

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... DSP56301 Technical Data, Rev MHz 100 MHz Unit Min Max Min Max + 24.7 — 55.9 + 21.5 — 46.5 31.3 — 25.0 — 31.3 — 25.0 — — 22.2 — 19.6 4.3 — 3.4 — 7.4 — 5.9 — 302 332 331 Freescale Semiconductor ...

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... HWR HDRQ Figure 2-28. HRW HDS HIRQ 332 HDS HRD HWR HRST HI32 Outputs Freescale Semiconductor 336 305 334 333 Universal Bus Mode DMA Access Timing 303 Figure 2-29. HRW to HDS Timing 326 Figure 2-30. HIRQ Pulse Width (HIRH = 0) 346 Figure 2-31. ...

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... HD[23–0] HSAK 342 HDBDR HDBEN 338 2-38 306 309 307 310 322 321 323 311 Valid (Output) 312 313 318 343 339 Figure 2-32. Read Timing DSP56301 Technical Data, Rev. 10 324 325 315 314 319 345 344 341 340 Freescale Semiconductor ...

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... HDS HRD HBS 320 HTA HD[23–0] HSAK HDBDR 338 HDBEN CLKOUT HBS CLKOUT HDS HRD HWR Figure 2-35. Freescale Semiconductor 306 309 307 310 322 321 323 324 Valid (Input) 318 316 339 Figure 2-33. Write Timing 347 Figure 2-34. ...

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... Freescale Semiconductor Unit μ ...

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... Clock low period 413 Clock high period 414 Output data setup to clock rising edge (internal clock) 415 Output data hold after clock rising edge (internal clock) Freescale Semiconductor 357 356 Figure 2-37. PCI Reset Timing Table 2-21. SCI Timing Symbol Expression 2 8 × ...

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... Data Valid a) Internal Clock 400 402 401 407 408 Data Valid 409 410 Data Valid b) External Clock SCI Synchronous Mode Timing DSP56301 Technical Data, Rev MHz 100 MHz Unit Min Max Min Max ) C. is determined by the SCI clock ACC Freescale Semiconductor ...

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... FSR input (bl, wr) high before RXC falling edge 442 FSR input (wl) high before RXC falling edge 443 FSR input hold time after RXC falling edge 444 Flags input setup before RXC falling edge Freescale Semiconductor 411 412 414 Data Valid SCI Asynchronous Mode Timing Table 2-22. ...

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... Freescale Semiconductor Unit ...

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... If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay (0.5 × Freescale Semiconductor Table 2-22. ESSI Timings (Continued) Symbol Expression = DSP56301 Technical Data, Rev Electrical Characteristics ...

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... Normal mode, the output flag state is asserted for the entire frame period. 2-46 430 432 446 447 450 454 454 452 First Bit 459 457 453 461 458 460 462 Figure 2-40. ESSI Transmitter Timing DSP56301 Technical Data, Rev. 10 451 455 Last Bit 456 461 See Note Freescale Semiconductor ...

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... Synchronous timer delay time from CLKOUT rising edge to the external memory access address out valid caused by first interrupt instruction execution 484 CLKOUT rising edge to TIO (Output) assertion • Minimum • Maximum Freescale Semiconductor 430 431 432 433 434 437 439 First Bit ...

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... MHz 100 MHz Min Max Min Max — 31.0 — 8.5 0.0 — 0.0 — 8.5 — 8.5 — 0.0 — 0.0 — 84.4 — 67.5 — C Freescale Semiconductor Unit ns ns Unit ...

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... TRST setup time to TCK low = 3.3 V ± 0 −40°C to +100 °C, C Notes All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. Freescale Semiconductor 492 493 Valid 494 Figure 2-45. GPIO Timing Table 2-25. JTAG Timing 1,2 Characteristics × ...

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... Output Data Valid Boundary Scan (JTAG) Timing Diagram 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid Test Access Port Timing Diagram DSP56301 Technical Data, Rev. 10 502 V M 503 V IH 505 V IH 509 Freescale Semiconductor ...

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... Response time when DSP56301 is executing NOP instructions from internal memory 516 Debug acknowledge assertion time = 3.3 V ± 0 −40°C to +100 °C, C Note Freescale Semiconductor 513 512 Figure 2-49. TRST Timing Diagram Table 2-26. OnCE Module Timing Expression × 3), 1/(T C max: 22.0 MHz 1.5 × ...

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... Specifications 2-52 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... The lead-free package requires a higher solder flow temperature than the lead-bearing device. Refer to Lead-Free BGA Solder Joint Assembly Evaluation (EB635) for manufacturing considerations when incorporating lead-free package devices into a design. Freescale Semiconductor DSP56301 Technical Data, Rev 3-1 ...

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... MODA D23 D22 D21 V CCD GND D D20 D19 D18 D17 D16 D15 V CCD GND D D14 D13 D12 D11 D10 D9 V CCD GND D V CCQ GND CCD GND A23 A22 V CCA GND A A21 A20 A19 A18 V CCA GND A A17 A16 Freescale Semiconductor ...

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... GND A A21 A20 A19 A18 V CCA GND A A17 A16 Figure 3-2. Freescale Semiconductor (Bottom View) DSP56301 Thin Quad Flat Pack (TQFP), Bottom View DSP56301 Technical Data, Rev. 10 TQFP Package Description 157 NC NC HAD11 HAD10 HAD9 HAD8 HC0 HAD7 HAD6 HAD5 HAD4 ...

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... GND Q 28 BCLK GND CCA GND CCA GND CCA 45 A10 46 A11 47 A12 48 A13 49 GND CCA DSP56301 Technical Data, Rev. 10 Pin Signal Name No. 51 A14 52 A15 A16 56 A17 57 GND CCA 59 A18 60 A19 61 A20 62 A21 63 GND CCA 65 A22 66 A23 GND CCD Freescale Semiconductor ...

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... CCD 90 D15 91 D16 92 D17 93 D18 94 D19 95 D20 96 GND CCD 98 D21 99 D22 100 D23 Freescale Semiconductor Pin Signal Name No. 101 MODA/IRQA 102 MODB/IRQB 103 NC 104 NC 105 MODC/IRQC 106 MODD/IRQD 107 HAD31 or HD23 108 HAD30 or HD22 109 HAD29 or HD21 110 HAD28 or HD20 111 ...

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... Signal Name No. 191 SRD0 or PC4 192 SCK0 or PC3 193 V CCS 194 GND S 195 STD0 or PC5 196 SC00 or PC0 197 SC01 or PC1 198 SC02 or PC2 199 DE 200 TMS 201 TCK 202 TDI 203 TDO 204 TRST 205 BS 206 BL 207 NC 208 NC Freescale Semiconductor ...

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... A18 59 A19 A20 61 A21 62 A22 65 A23 AA0 AA1 AA2 20 Freescale Semiconductor DSP56301 TQFP Signal Identification by Name Signal Name AA3 BB BCLK BCLK CAS CLKOUT D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 1 D21 2 D22 D23 DSP56301 Technical Data, Rev. 10 ...

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... HC1 150 HC2 128 HC3 117 HCLK 148 HD0 162 HD1 161 HD10 125 HD11 124 HD12 121 HD13 120 HD14 119 HD15 118 HD16 116 HD17 115 HD18 114 HD19 113 HD2 160 HD20 110 HD21 109 Freescale Semiconductor ...

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... HGNT 149 HIDSEL 129 HINTA 181 HIRDY 133 HIRQ 142 HLOCK 140 HPAR 145 HPERR 141 HRD 129 HREQ 146 Freescale Semiconductor Pin Signal Name No. HRST/HRST 147 HRW 139 HSAK 138 HSERR 142 HSTOP 139 HTA 146 HTRDY 134 HWR 139 ...

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... CCD V 81 CCD V 89 CCD V 97 CCD V 111 CCH V 122 CCH V 135 CCH V 144 CCH V 156 CCH V 169 CCH V 3 CCN V 18 CCN V 11 CCP V 25 CCQ V 79 CCQ V 131 CCQ V 182 CCQ V 179 CCS V 193 CCS WR 22 XTAL 24 Freescale Semiconductor ...

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... TQFP Package Mechanical Drawing 0 208 Pin 1 ident 0. View AA Figure 3-3. DSP56301 Mechanical Information, 208-pin TQFP Package Freescale Semiconductor 0 TIPS 157 156 M view 105 104 View AA Seating plane ( 0.08 ( 0.25 Gage plane ( (Z) CASE 998-01 DSP56301 Technical Data, Rev. 10 ...

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... MODC NC MODB D23 MODA D22 D21 GND V D18 D19 D20 D17 CC GND V D12 D15 D16 D14 CC GND V D11 D9 D13 D8 CC GND D10 GND GND A19 A21 A22 A23 A16 A17 A20 A12 NC A15 NC A18 A6 A9 A11 A14 A10 A13 NC Freescale Semiconductor ...

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... V CC A18 NC A15 NC A12 NC NC A14 A11 A9 NC A13 A10 A7 Figure 3-5. DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View Freescale Semiconductor Bottom View HAD20 HAD17 HAD16 HIRDY HPERR HPAR HIDSEL HDEV HSERR HRST HAD19 HC2 SEL H HC3 HAD21 HAD18 ...

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... HSTOP or HWR/HRW D8 HTRDY, HDBEN, or PB20 D10 V CC D11 V CC D12 HAD28 or HD20 D13 MODC/IRQC D14 NC D15 MODB/IRQB D16 D23 E1 HAD2, HA5, or PB2 E2 HAD4, HA7, or PB4 E3 HAD6, HA9, or PB6 E4 HC0/HBE0, HA0, or PB16 E10 V CC E11 V CC E12 V CC E13 V CC Freescale Semiconductor ...

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... GND F12 V CC F13 D18 F14 D19 F15 D20 F16 D17 G1 TIO1 G2 RXD or PE0 G3 TIO2 GND Freescale Semiconductor Pin Signal Name No. G7 GND G8 GND G9 GND G10 GND G11 GND G12 V CC G13 D12 G14 D15 G15 D16 G16 D14 H1 SCLK or PE2 ...

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... N9 A1 N10 A2 DSP56301 Technical Data, Rev. 10 Pin Signal Name No. N11 V CC N12 V CC N13 A16 N14 A17 N15 A20 N16 NC P1 TRST AA0/RAS0 P4 CLKOUT P5 PINIT/NMI P6 GND AA3/RAS3 P9 EXTAL P10 A5 P11 A8 P12 A12 P13 NC P14 A15 P15 NC P16 A18 AA1/RAS1 Freescale Semiconductor ...

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... A2, B1, and B2 — pins A15, B15, B16, C14, C15, C16, and D14 — pins N3, R1, R2, and T2 — pins N16, P13, P15, R15, R16, and T15 Do not connect any line, component, trace, or via to these pins. Freescale Semiconductor Pin Signal Name No. R13 ...

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... GND G13 GND H15 GND G16 GND G14 GND G15 GND F16 GND F13 GND F14 GND L15 GND F15 GND E16 GND Freescale Semiconductor Pin No. E15 D16 K14 K16 J14 K15 J16 H16 H14 M2 P9 F10 F11 G10 G11 G6 G7 ...

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... GND GND GND GND K10 GND K11 GND GND GND GND GND L10 GND L11 GND GND GND GND GND P1 GND P HA0 HA1 Freescale Semiconductor Signal Name H7 HA10 H8 HA2 H9 HA3 HA4 HA5 J6 HA6 J7 HA7 J8 HA8 J9 HA9 HAD0 HAD1 K6 HAD10 K7 HAD11 K8 HAD12 ...

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... DSP56301 Technical Data, Rev. 10 Pin Signal Name No. A9 HWR A5 IRQA A7 IRQB D8 IRQC B7 IRQD A6 MODA B8 MODB C8 MODC B4 MODD Freescale Semiconductor Pin No. D7 E14 D15 D13 C13 E14 D15 D13 C13 A15 A2 B1 B15 B16 B2 C14 C15 C16 D14 N16 N3 P13 P15 R1 R2 ...

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... NC NC T15 NMI PB0 PB1 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 C11 PB2 PB20 PB21 PB22 PB23 PB3 PB4 PB5 Freescale Semiconductor Signal Name PB6 PB7 T2 PB8 PB9 P5 PC0 F2 PC1 F1 PC2 D4 PC3 C2 PC4 C3 PC5 C4 PCAP B3 PD0 A3 PD1 ...

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... N16, P13, P15, R15, R16, and T15 Do not connect any line, component, trace, or via to these pins. 3-22 Signal Name DSP56301 Technical Data, Rev. 10 Pin Signal Name No G12 H12 J12 V CC J13 K12 V CC K13 L12 V CCP L13 WR L5 XTAL Freescale Semiconductor Pin No. M10 M11 M12 N11 N12 ...

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... MAP-BGA Package Mechanical Drawing Figure 3-6. DSP56301 Mechanical Information, 252-pin MAP-BGA Package Freescale Semiconductor Notes: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls ...

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... Packaging 3-24 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to the point at which the leads attach to the case. Freescale Semiconductor , in °C can be obtained from this equation × ...

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... V CC and circuits. GND , , ). TMS GND CCP P and RESET DSP56301 Technical Data, Rev – T )/P . This value gives a better estimate pin on the DSP and from the V CC and GND , , IRQA IRQB IRQC , and pins. GND P1 . TRST Freescale Semiconductor pins GND , , IRQD ...

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... DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current-per-MIPS value. Freescale Semiconductor × Example 1. Current Consumption – ...

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... The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. 4-4 ⁄ ⁄ MHz = I – – typF2 typF1 is 0.5 percent. If the rate of change of the frequency of EXTAL DSP56301 Technical Data, Rev slow EXTAL Freescale Semiconductor ...

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... Area w.s (SSRAM) ; Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL; XTAL disable ; PLL enable ; CLKOUT disable ; ;Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 Freescale Semiconductor * * DSP56301 Technical Data, Rev A-1 ...

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... PROG_END nop nop XDAT_START ; org x:0 dc $262EB9 dc $86F2FE dc $E56A5F dc $616CAC dc $8FFD75 dc $9210A dc $A06D7B dc $CEA798 dc $8DFBF1 dc $A063D6 A-2 ; ebd y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-3 ...

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... A-4 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... M_DTXS EQU $FFFFCD ; DSP SLAVE TRANSMIT DATA FIFO (DTXS) M_DTXM EQU $FFFFCC; DSP MASTER TRANSMIT DATA FIFO (DTXM) M_DRXR EQU $FFFFCB; DSP RECEIVE DATA FIFO (DRXR) M_DPSR EQU $FFFFCA; DSP PCI STATUS REGISTER (DPSR) Freescale Semiconductor PLL control reg DSP56301 Technical Data, Rev. 10 A-5 ...

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... Host PCI Address Register Bit Flags M_ARL EQU $00ffff; DSP PCI Transaction Address (Low) M_C EQU $0f0000; PCI Bus Command M_BE EQU $f00000; PCI Byte Enables ; DSP Status Register Bit Flags M_HCP EQU 0 ; Host Command pending A-6 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... Word Select 0 M_WDS1 EQU 1 ; Word Select 1 M_WDS2 EQU 2 ; Word Select 2 M_SSFTD EQU 3 ; SCI Shift Direction M_SBK EQU 4 ; Send Break M_WAKE EQU 5 ; Wakeup Mode Select M_RWU EQU 6 ; Receiver Wakeup Enable M_WOMS EQU 7 ; Wired-OR Mode Select Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-7 ...

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... M_TSR1 EQU $FFFFA9; SSI1 Time Slot Register M_RX1 EQU $FFFFA8; SSI1 Receive Data Register M_SSISR1 EQU $FFFFA7; SSI1 Status Register M_CRB1 EQU $FFFFA6; SSI1 Control Register B M_CRA1 EQU $FFFFA5; SSI1 Control Register A M_TSMA1 EQU $FFFFA4; SSI1 Transmit Slot Mask Register A A-8 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... Transmitter Underrun Error FLag M_ROE EQU 5 ; Receiver Overrun Error Flag M_TDE EQU 6 ; Transmit Data Register Empty M_RDF EQU 7 ; Receive Data Register Full ; SSI Transmit Slot Mask Register A M_SSTSA EQU $FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15) Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-9 ...

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... DMA3 Interrupt Priority Level (low) M_D3L1 EQU 19 ; DMA3 Interrupt Priority Level (high) M_D4L EQU $300000; DMA4 Interrupt priority Level Mask M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low) M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high) A-10 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... M_TPCR EQU $FFFF82 ; TIMER Prescalar Count Register ; Timer Control/Status Register Bit Flags M_TE EQU 0 ; Timer Enable M_TOIE EQU 1 ; Timer Overflow Interrupt Enable M_TCIE EQU 2 ; Timer Compare Interrupt Enable Freescale Semiconductor Interrupt Priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) DSP56301 Technical Data, Rev. 10 A-11 ...

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... M_DCR1 EQU $FFFFE8; DMA1 Control Register ; Register Addresses Of DMA2 M_DSR2 EQU $FFFFE7; DMA2 Source Address Register M_DDR2 EQU $FFFFE6; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5; DMA2 Counter M_DCR2 EQU $FFFFE4; DMA2 Control Register ; Register Addresses Of DMA4 A-12 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... DMA Channel Transfer Done Status 3 M_DTD4 EQU 4 ; DMA Channel Transfer Done Status 4 M_DTD5 EQU 5 ; DMA Channel Transfer Done Status 5 M_DACT EQU 8 ; DMA Active State M_DCH EQU $E00 ; DMA Active Channel Mask (DCH0-DCH2) M_DCH0 EQU 9 ; DMA Active Channel 0 Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-13 ...

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... DRAM Control Register M_BCW EQU $ Page Wait States Bits Mask (BCW0-BCW1) M_BRW EQU $C ; Out Of Page Wait States Bits Mask (BRW0-BRW1) M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1) M_BPLE EQU 11 ; Page Logic Enable A-14 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... M_BEN EQU 10 ; Burst Enable M_TAS EQU Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_XYS EQU 16 ; Stack Extension space select bit in OMR. M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR. M_EOV EQU 18 ; Extended stack OVerflow flag in OMR. Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-15 ...

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... I_TIM0OF EQU I_VEC+$26 A-16 ; Hardware RESET ; Stack Error ; Illegal Instruction ; Debug Request ; Trap ; Non Maskable Interrupt ; IRQA ; IRQB ; IRQC ; IRQD ; DMA Channel 0 ; DMA Channel 1 ; DMA Channel 2 ; DMA Channel 3 ; DMA Channel 4 ; DMA Channel 5 ; TIMER 0 compare ; TIMER 0 overflow DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... I_HST EQU I_VEC+$6E I_HPMA EQU I_VEC+$70 I_HCNMI EQU I_VEC+$72 ;------------------------------------------------------------------------ ; INTERRUPT ENDING ADDRESS ;------------------------------------------------------------------------ I_INTEND EQU I_VEC+$FF Freescale Semiconductor ; TIMER 1 compare ; TIMER 1 overflow ; TIMER 2 compare ; TIMER 2 overflow ; ESSI0 Receive Data ; ESSI0 Receive Data With Exception Status ; ESSI0 Receive last slot ; ESSI0 Transmit data ...

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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 1996, 2006. Core Solder Spheres Order Number 80 Lead-free DSP56301AG80 Lead-bearing DSP56301PW80 100 Lead-free DSP56301AG100 Lead-bearing DSP56301PW100 ...