ADSP-21369KSZ-1A Analog Devices Inc, ADSP-21369KSZ-1A Datasheet - Page 48

• Manufacturer Part Number: ADSP-21369KSZ-1A
• Description: IC DSP 32BIT 266 MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant
• Other names: Q2886718

ADSP-21367/ADSP-21368/ADSP-21369
OUTPUT DRIVE CURRENTS
Figure 38
ers and
SDCLK output drivers. The curves represent the current drive
capability of the output drivers as a function of output voltage.
- 105
- 20
- 30
- 40
- 10
- 15
- 30
- 45
- 60
- 75
- 90
Figure 39
40
30
20
10
45
0
75
60
30
15
0
0
shows typical I-V characteristics for the output driv-
Figure 39. SDCLK1–0 Drive at Junction Temperature
0
Figure 38. Typical Drive at Junction Temperature
3 .47 V, - 4 5°C
3.3 V, 2 5°C
V
OL
0.5
0.5
shows typical I-V characteristics for the
3.11V, 125°C
3.47V, - 45°C
SWEEP (V
1.0
3 .1 3 V, 12 5 °C
S W EE P (V
1.0
V
O L
3.11V, 125°C
3.1 3V, 1 25 °C
1.5
DDEXT
3.1 3V, 1 05 °C
1.5
D D EX T
) VOLTAGE (V)
V
2.0
V
O H
3 .1 3 V, 10 5° C
OH
) VOL TAG E (V )
2.0
2.5
3.3V, 25°C
2.5
3.0
3.11V, 105°C
3 .47 V, - 45 °C
3.3V, 25°C
Rev. E | Page 48 of 60 | July 2009
3.47V, - 45°C
3.3 V, 25 °C
3.5
3.0
3.11V, 105°C
3.5
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 14 on Page 23
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in
Timing is measured on signals when they cross the 1.5 V level as
described in
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see
Figure 47
with load capacitance. The graphs of
Figure 47
cal Output Delay vs. Load Capacitance and Typical Output Rise
Time (20% to 80%, V = Min) vs. Load Capacitance.
1.5V
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
4pF
OUTPUT
Figure 40. Voltage Reference Levels for AC Measurements
Figure 41. Equivalent Device Loading for AC Measurements
INPUT
show graphically how output delays and holds vary
may not be linear outside the ranges shown for Typi-
OR
Figure
70
50
400
2pF
1.5V
Figure
40. All delays (in nanoseconds) are mea-
through
(Includes All Fixtures)
45
0.5pF
40.
TESTER PIN ELECTRONICS
Table 42 on Page
ZO = 50 (impedance)
TD = 4.04
Figure
Figure 42
T1
41).
1.18 ns
47. These include
through
Figure 46
1.5V
OUTPUT
DUT
and