ADSP-2196MBCA-140 Analog Devices Inc, ADSP-2196MBCA-140 Datasheet - Page 4

• Manufacturer Part Number: ADSP-2196MBCA-140
• Description: IC DSP CONTROLLER 16BIT 144MBGA
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2196MBCA-140

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 140MHz
• Non-volatile Memory: ROM (48 kB)
• On-chip Ram: 40kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-MBGA, 144-Mini-BGA

ADSP-2196
General Note
This data sheet provides preliminary information for the
ADSP-2196 Digital Signal Processor.
GENERAL DESCRIPTION
The ADSP-2196 DSP is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.
The ADSP-2196 combines the ADSP-219x family base
architecture (three computational units, two data address
generators, and a program sequencer) with three serial
ports, two SPI-compatible ports, one UART port, a DMA
controller, three programmable timers, general-purpose
Programmable Flag pins, extensive interrupt capabilities,
and on-chip program and data memory spaces.
The ADSP-2196 architecture is code-compatible with
ADSP-218x family DSPs. Although the architectures are
compatible, the ADSP-2196 architecture has a number of
enhancements over the ADSP-218x architecture. The
enhancements to computational units, data address gener-
ators, and program sequencer make the ADSP-2196 more
flexible and even easier to program than the
ADSP-218x DSPs.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an
immediate 8-bit, two’s-complement value and base address
registers for easier implementation of circular buffering.
The ADSP-2196 integrates 32K words of on-chip memory
configured as 8K words (24-bit) of program RAM, 8K
words (16-bit) of data RAM, and 16K words (24-bit) of
program ROM. Power-down circuitry is also provided to
meet the low power needs of battery-operated portable
equipment. The ADSP-2196 is available in 144-lead LQFP
and mini-BGA packages.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2196 operates with a 6.25 ns instruction cycle time
(160 MIPS). All instructions, except two multiword
instructions, can execute in a single DSP cycle.
The ADSP-2196’s flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, the ADSP-2196 can:
• Generate an address for the next instruction fetch
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
These operations take place while the processor
continues to:
• Receive and transmit data through two serial ports
• Receive and/or transmit data from a Host
• Receive or transmit data through the UART
4
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
For current information contact Analog Devices at 800/262-5643
• Receive or transmit data over two SPI ports
• Access external memory through the external memory
• Decrement the timers
DSP Core Architecture
The ADSP-2196 instruction set provides flexible data
moves and multifunction (one or two data moves with a
computation) instructions. Every single-word instruction
can be executed in a single processor cycle. The ADSP-2196
assembly language uses an algebraic syntax for ease of
coding and readability. A comprehensive set of development
tools supports program development.
The functional block diagram
ture of the ADSP-219x core. It contains three independent
computational units: the ALU, the multiplier/accumulator
(MAC), and the shifter. The computational units process
16-bit data from the register file and have provisions to
support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs sin-
gle-cycle multiply, multiply/add, and multiply/subtract
operations. The MAC has two 40-bit accumulators, which
help with overflow. The shifter performs logical and arith-
metic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword
and block floating-point representations.
Register-usage rules influence placement of input and
results within the computational units. For most operations,
the computational units’ data registers act as a data register
file, permitting any input or result register to provide input
to any unit for a computation. For feedback operations, the
computational units let the output (result) of any unit be
input to any unit on the next cycle. For conditional or mul-
tifunction instructions, there are restrictions on which data
registers may provide inputs or receive results from each
computational unit. For more information, see the
ADSP-219x DSP Instruction Set Reference.
A powerful program sequencer controls the flow of instruc-
tion execution. The sequencer supports conditional jumps,
subroutine calls, and low interrupt overhead. With internal
loop counters and loop stacks, the ADSP-2196 executes
looped code with zero overhead; no explicit jump instruc-
tions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
16-bit address pointers. Whenever the pointer is used to
access data (indirect addressing), it is pre- or post-modified
by the value of one of four possible modify registers. A length
value and base address may be associated with each pointer
to implement automatic modulo addressing for circular
buffers. Page registers in the DAGs allow circular addressing
interface
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