ADSP-2185LKST-115 Analog Devices Inc, ADSP-2185LKST-115 Datasheet - Page 11

• Manufacturer Part Number: ADSP-2185LKST-115
• Description: IC DSP CONTROLLER 16BIT 100LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2185LKST-115

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 28.8MHz
• Non-volatile Memory: External
• On-chip Ram: 80kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP

See
flag and composite control register and the system
control register.
Byte Memory Select
The ADSP-218xL’s BMS disable feature combined with the
CMS pin allows use of multiple memories in the byte memory
space. For example, an EPROM could be attached to the BMS
select, and a flash memory could be connected to CMS. Because
at reset BMS is enabled, the EPROM would be used for booting.
After booting, software could disable BMS and set the CMS sig-
nal to respond to BMS, enabling the flash memory.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide,
external memory space used to store programs and data. Byte
memory is accessed using the BDMA feature. The byte memory
space consists of 256 pages, each of which is 16K
The byte memory space on the ADSP-218xL series supports
read and write operations as well as four different data formats.
The byte memory uses data bits 15–8 for data. The byte mem-
ory uses data bits 23–16 and address bits 13–0 to create a 22-bit
address. This allows up to a 4 megabit
or RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register.
SPO RT0 ENABL E
0 = DISABL E
1 = ENABL E
RESERVED
N OTE: RESERVED BITS ARE SHO WN O N A GRAY FIELD . THESE B ITS
R ESERVED
SPO RT1 C ONF IGURE
0 = FI, FO , IRQ0, IRQ1, SCLK
1 = SPORT1
Figure 9
15 14 13 12 11 10
0
15 14 13 12 11 10 9
SET T O 0
SPORT 1 ENABLE
0 = DISABLE
1 = ENABLE
0
Figure 9. Programmable Flag and Composite Control Register
1
BMWAIT
0
SHOUL D ALW AYS BE WR ITTEN W ITH Z EROS.
PROGRAMMABLE FLAG AND COMPOSITE
1
0
and
1
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
0
1
0
Figure 10
Figure 10. System Control Register
CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
0
1
SELECT CONTROL
SYSTEM CONTROL
RESERVED,ALW AYS
9
1
0
8
1
8
0
SET TO 0
for illustration of the programmable
7
0
7
0
6
0
DISABLE BMS
0 = ENABL E BMS
1 = DISAB LE BMS
6
0
5
0
5
0
PFTYPE
0 = INPUT
1 = OUTPUT
4
0
4
0
3
0
3
0
8 (32 megabit) ROM
2
0
PW AIT
PRO GRAM MEMOR Y
W AIT ST ATES
2
1
1
0
1
1
0
0
0
1
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C | Page 11 of 48 | January 2008
8 bits.
DM(0x3FE6)
DM(0x3F FF)
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller
and storing of program instructions and data using the byte
memory space. The BDMA circuit is able to access the byte
memory space while the processor is operating normally and
steals only one DSP cycle per 8-, 16-, or 24-bit word transferred.
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number of
8-bit accesses are done from the byte memory space to build the
word size selected.
the BDMA circuit.
Table 7. Data Formats
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations. The source or destination
of a BDMA transfer is always on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
BTYPE
00
01
10
11
15 14 13 12 11 10
0
0
0
BMPAGE
0
Internal Memory
Space
Program memory
Data memory
Data memory
Data memory
0
Figure 11. BDMA Control Register
0
Table 7
BDMA CONTROL
9
0
8
0
(SEE TABLE 12)
shows the data formats supported by
7
0
OVERLAY
BDMA
6
0
BITS
5
0
(Figure
Word Size
24
16
8
8
4
0
3
1
2
0
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
11) allows loading
1
BTYPE
0
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
0
0
Alignment
Full word
Full word
MSBs
LSBs
DM (0x3FE3)