ADSP-2184NKST-320 Analog Devices Inc, ADSP-2184NKST-320 Datasheet - Page 19

• Manufacturer Part Number: ADSP-2184NKST-320
• Description: IC DSP CONTROLLER 16BIT 100LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2184NKST-320

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 20kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP

Table 9. Common-Mode Pins (Continued)
1
2
MEMORY INTERFACE PINS
ADSP-218xN series members can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities.
Table 10. Full Memory Mode Pins (Mode C = 0)
Table 11. Host Mode Pins (Mode C = 1)
1
TERMINATING UNUSED PINS
Table 12
pins.
Table 12. Unused Pin Terminations
Pin Name
V
V
GND
EZ-Port
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector
SPORT configuration determined by the DSP System Control Register. Software configurable.
Pin Name
A13–0
D23–0
Pin Name
IAD15–0
A0
D23–8
IWR
IRD
IAL
IS
IACK
In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
Pin Name
XTAL
CLKOUT
A13–1 or
IAD12–0
A0
address when the pin is asserted, either by external devices or set as a programmable flag.
DDINT
DDEXT
shows the recommendations for terminating unused
1
No. of Pins
14
24
No. of Pins
16
1
16
1
1
1
1
1
No. of Pins
4
7
20
9
I/O
3-State
(Z)
O
O
O (Z)
I/O (Z)
O (Z)
2
I/O
O
I/O
I/O
I/O
O
I/O
I
I
I
I
O
Function
Address Output Pins for Program, Data, Byte, and I/O Spaces
Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory
Addresses.)
Function
IDMA Port Address/Data Bus
Address Pin for External I/O, Program, Data, or Byte Access
Data I/O Pins for Program, Data, Byte, and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configurable in Mode D; Open Drain
I/O
I
I
I
I/O
Reset
State
O
O
Hi-Z
Hi-Z
Hi-Z
Rev. A | Page 19 of 48 | August 2006
Hi-Z
BR, EBR
IS
BR, EBR
Function
Internal V
External V
Ground (BGA)
For Emulation Use
3
Caused By
DD
DD
(1.8 V) Power (BGA)
(1.8 V, 2.5 V, or 3.3 V) Power (BGA)
The operating mode is determined by the state of the Mode C
pin during RESET and cannot be changed while the processor is
running.
pins of the DSP during either of the two operating modes (Full
Memory or Host). A signal in one table shares a pin with a sig-
nal from the other table, with the active signal determined by
the mode that is set. For the shared pins and their alternate sig-
nals (e.g., A4/IAD3), refer to the package pinouts in
Page 41
and
Unused Configuration
Float
Float
Float
Float
Float
Table 10
Table 28 on Page
4
and
Table 11
1
43.
list the active signals at specific
ADSP-218xN
Table 27 on