ADSP-2171BS-133 Analog Devices Inc, ADSP-2171BS-133 Datasheet
ADSP-2171BS-133
Specifications of ADSP-2171BS-133
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ADSP-2171BS-133 Summary of contents
Page 1
... ALU constants, new multiplication instruction (x squared), biased rounding, and global interrupt masking, for increased flexibility. The ADSP-217x also has a Bus Grant Hang Logic (BGH) feature. The ADSP-217x provides 2K words (24-bit) of program RAM and 2K words (16-bit) of data memory ...
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... ADSP-2100 Family Assembler Tools & Simulator Manual. ARCHITECTURE OVERVIEW Figure overall block diagram of the ADSP-217x. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provi- sions to support multiprecision computations. The ALU per- forms a standard set of arithmetic and logic operations ...
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... DMD) share a single external data bus. Program memory can store both instructions and data, permit- ting the ADSP-217x to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP- 217x can fetch an operand from on-chip program memory and the next instruction in the same cycle ...
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... O Powerdown acknowledge pin Host Interface Port The ADSP-217x host interface port is a parallel I/O port that al- lows for an easy connection to a host processor. Through the HIP, the ADSP-217x can be used as a memory-mapped periph- eral to a host computer. The HIP can be thought area ...
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... Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected.The powerdown interrupt is nonmaskable. The ADSP-217x masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect autobuffering. ...
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... Clock Signals The ADSP-217x can be clocked by either a crystal TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during normal opera- tion ...
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... CLKODIS bit in the SPORT0 Autobuffer Control Reg- ister, DM[0x3FF3]. Reset The RESET signal initiates a master reset of the ADSP-217x. The RESET signal must be asserted during the power-up se- quence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock REV ...
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... TO 1 HIP Booting DURING RESET) The ADSP-217x can also boot programs through its Host Inter- face Port. If BMODE = 1 and MMAP = 0, the ADSP-217x boots from the HIP. If BMODE = 0, the ADSP-217x boots 27FF through the data bus (in the same way as the ADSP-2101), as 2800 described above in “ ...
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... ROM location 0x0800 Ordering Procedure for ADSP-2172 Processors To place an order for a custom ROM-coded ADSP-2172 pro- cessor, you must: 1. Complete the following forms contained in the ADSP ROM Ordering Package, available from your Analog Devices sales representative: ...
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... PMS, DMS, BMS, RD, WR output drivers, asserting the bus grant (BG) signal, and halting program execution. If the Go Mode is enabled, the ADSP-217x will not halt pro- gram execution until it encounters an instruction that requires an external memory access. If the ADSP-217x is performing an external memory access ...
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... SS Shifter Input Sign SPORT0 Enable 1 = enabled disabled SPORT1 Enable 1 = enabled disabled SPORT1 Configure 1 = serial port 0 = FI, FO, IRQ0, IRQ1, SCLK REV. A ADSP-2171/ADSP-2172/ADSP-2173 SSTAT (Read-Only MSTAT Data Register Bank Select 0 = primary secondary Bit Reverse Mode Enable (DAG1) ALU Overflow Latch Mode Enable AR Saturation Mode Enable ...
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... ADSP-2171/ADSP-2172/ADSP-2173 DWAIT4 SPORT0 Multichannel Receive Word Enable Registers 1 = Channel Enabled 0 = Channel Ignored 0x3FFA 0x3FF9 Multichannel Enable MCE Internal Serial Clock Generation ISCLK Receive Frame Sync Required RFSR Receive Frame Sync Width RFSW Multichannel Frame Delay MFD Only If Multichannel Mode Enabled Transmit Frame Sync Required TFSR ...
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... Flag Out (Read Only) Internal Serial Clock Generation ISCLK Receive Frame Sync Required RFSR Receive Frame Sync Width RFSW Transmit Frame Sync Required TFSR Transmit Frame Sync Width TFSW ITFS Internal Transmit Frame Sync Enable REV. A ADSP-2171/ADSP-2172/ADSP-2173 SPORT0 SCLKDIV Serial Clock Divide Modulus 0x3FF5 ...
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... ADSP-2171/ADSP-2172/ADSP-2173 SPORT1 SCLKDIV Serial Clock Divide Modulus 0x3FF1 XTALDIS XTAL Pin Drive Disable during Powerdown 1 = disabled enabled (disable XTAL pin when no external crystal connected) XTALDELAY 4096 Cycle Delay Enable 1 = delay delay PDFORCE Powerdown Force PUCR Powerup Context Reset Enable 1 = soft reset (context clear), ...
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... Programs may need to be relo- 00-0001-7FFF cated to utilize internal memory and conform to the ADSP- 217x’s interrupt vector and reset vector map. Sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle ...
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... Syntax: ENA INTS; Description: Executing the ENA INTS instruction allows all unmasked interrupts to be serviced again. Interrupt Disable The ADSP-217x supports an interrupt disable instruction. The instruction source code is specified as follows: Syntax: DIS INTS; Description: Reset enables interrupt servicing. Executing the DIS INTS instruction causes all interrupts to be masked without changing the contents of the IMASK register ...
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... Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, HD0-HD15/HAD0-HAD15 BR, CLKIN Active (to force three-state condition). 9 Idle refers to ADSP-2171/ADSP-2172 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V device operation with CLKOUT disabled. 10 Current reflects device operating with no output loads. ...
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... The ADSP-217x features proprietary ESD protection circuitry to dissipate high energy discharges (Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-217x has been classified as a Class 1 device. Proper ESD precautions are recommended to avoid performance degradation or loss of function- ality ...
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... ADSP-2171/ADSP-2172 Parameter Clock Signals t is defined as 0.5 t The ADSP-2171/ADSP-2172 uses an CK CKI. input clock with a frequency equal to half the instruction rate; a clock (which is equivalent to 60 ns) yields processor cycle 16.67 MHz input (equivalent to 33 MHz). t range of 0.5 t period should be substituted for all relevant CKI timing parameters to obtain specification value ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Interrupts and Flags Timing Requirement: t IRQx or FI Setup before CLKOUT Low IFS t IRQx or FI Hold after CLKOUT High IFH Switching Characteristic: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay from CLKOUT Low FOD NOTES 1 If IRQx and FI inputs meet t and t setup/hold requirements, they will be recognized during the current clock cycle ...
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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Memory Read Timing Requirement Low to Data Valid RDD t A0–A13, PMS, DMS, BMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristic Pulse Width RP t CLKOUT High to RD Low CRD t A0–A13, PMS, DMS, BMS Setup before RD Low ...
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... CWR t A0–A13, DMS, PMS, Setup before WR Deasserted AW t A0–A13, DMS, PMS Hold after WR Deasserted WRA t WR High Low WWR w = wait states CLKOUT A0–A13 DMS, PMS REV. A ADSP-2171/ADSP-2172/ADSP-2173 Min 0.5 t – 0.25t – 0.5t – 0.25t – 0.25t – 0.25t – ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Serial Ports Timing Requirement: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristic: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid SCDV ...
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... Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low. HA2–0 HSEL Host Write Cycle HWR HACK HD15–0 HA2–0 HSEL Host Read Cycle HRD HACK HD15–0 Figure 14. Host Interface Port (HMD1 = 0, HMD0 = 0) REV. A ADSP-2171/ADSP-2172/ADSP-2173 Min ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Host Interface Port Separate Data and Address (HMD1 = 0) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t HA2–0, HRW Setup before Start of Write or Read HSU t Data Setup before End of Write HDSU t Data Hold after End of Write HWDH t HA2–0, HRW Hold after End of Write or Read ...
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... Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low. 5 End of Read = HRD High or HSEL High. ALE HSEL Host Write Cycle HWR HACK HD15–0 ALE Host Read Cycle HSEL HRD HACK HAD15–0 Figure 16. Host Interface Port (HMD1 = 1, HMD0 = 0) REV. A ADSP-2171/ADSP-2172/ADSP-2173 Min ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 Parameter Host Interface Port Multiplexed Data and Address (HMD1 = 1) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t ALE Pulse Width HALP t HAD15–0 Address Setup before ALE Low HASU t HAD15–0 Address Hold after ALE Low HAH t Start of Write or Read after ALE Low ...
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... INT 13 15 VALID FOR ALL TEMPERATURE GRADES. 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2 IDLE REFERS TO ADSP-2171 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OPERATING WITH CLKOUT DISABLED. 3 TYPICAL POWER DISSIPATION AT 5. IDLE N INSTRUCTION (CLOCK FREQUENCY REDUCTION). ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2171/ADSP-2172 CAPACITIVE LOADING Figures 19 and 20 show the capacitive loading characteristics of the ADSP-2171/ADSP-2172 4. 100 C – Figure 19. Typical Output Rise Time vs. Load Capacitance, C (at Maximum Ambient Operating Temperature) L +14 +12 + NOMINAL – 100 C – Figure 20. Typical Output Valid Delay or Hold vs. Load Capacitance, C (at Maximum Ambient Operating ...
Page 31
... Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, HD0-HD15/HAD0-HAD15 BR, CLKIN Active (to force three-state condition). 9 Idle refers to ADSP-2173 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V device operation with CLKOUT disabled. 10 Current reflects device operating with no output loads. ...
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... Also, use the switching characteristics to ensure any timing requirement of a device connected to the processor (such as memory) is satisfied. MEMORY REQUIREMENTS This chart links common memory device specification names and ADSP-2173 timing parameters for your convenience. Parameter Name Function t A0-A13, DMS, PMS ...
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... ADSP-2173 Parameter Clock Signals t is defined as 0.5 t The ADSP-2173 uses an input clock with CK CKI. a frequency equal to half the instruction rate; a 10.0 MHz input clock (which is equivalent to 100 ns) yields processor cycle (equivalent to 20 MHz). t values within the range of 0 period should be substituted for all relevant timing parameters to obtain specification value ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Interrupts and Flags Timing Requirement: t IRQx or FI Setup before CLKOUT Low IFS t IRQx or FI Hold after CLKOUT High IFH Switching Characteristic: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay from CLKOUT Low FOD NOTES 1 If IRQx and FI inputs meet t and t setup/hold requirements, they will be recognized during the current clock cycle ...
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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Memory Read Timing Requirement Low to Data Valid RDD t A0–A13, PMS, DMS, BMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristic Pulse Width RP t CLKOUT High to RD Low CRD t A0–A13, PMS, DMS, BMS Setup before RD Low ...
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... CWR t A0–A13, DMS, PMS, Setup before WR Deasserted AW t A0–A13, DMS, PMS Hold after WR Deasserted WRA t WR High Low WWR w = wait states CLKOUT A0–A13 DMS, PMS REV. A ADSP-2171/ADSP-2172/ADSP-2173 Min 0.5 t – 0.25t – 0.5t – 0.25t – 0.25t – 0.25t – ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Serial Ports Timing Requirement: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristic: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid SCDV ...
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... Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low. HA2–0 HSEL Host Write Cycle HWR HACK HD15–0 HA2–0 HSEL Host Read Cycle HRD HACK HD15–0 Figure 30. Host Interface Port (HMD1 = 0, HMD0 = 0) REV. A ADSP-2171/ADSP-2172/ADSP-2173 Min ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Host Interface Port Separate Data and Address (HMD1 = 0) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t HA2–0, HRW Setup before Start of Write or Read HSU t Data Setup before End of Write HDSU t Data Hold after End of Write HWDH t HA2–0, HRW Hold after End of Write or Read ...
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... Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low. ALE HSEL Host Write Cycle HWR HACK HD15–0 ALE HSEL Host Read Cycle HRD HACK HAD15–0 Figure 32. Host Interface Port (HMD1 = 1, HMD0 = 0) REV. A ADSP-2171/ADSP-2172/ADSP-2173 Min ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 Parameter Host Interface Port Multiplexed Data and Address (HMD1 = 1) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t ALE Pulse Width HALP t HAD15–0 Address Setup before ALE Low HASU t HAD15–0 Address Hold after ALE Low HAH t Start of Write or Read after ALE Low ...
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... VALID FOR ALL TEMPERATURE GRADES. INT 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2 IDLE REFERS TO ADSP-2173 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OPERATING WITH CLKOUT DISABLED. 3 TYPICAL POWER DISSIPATION AT 3. IDLE n INSTRUCTION (CLOCK FREQUENCY REDUCTION). ...
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... ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2173 CAPACITIVE LOADING Figures 35 and 36 show the capacitive loading characteristics of the ADSP-2173 3 100 C – Figure 35. Typical Output Rise Time vs. Load Capacitance, C (at Maximum Ambient Operating Temperature) L +14 +12 + NOMINAL - 100 C – Figure 36. Typical Output Valid Delay or Hold vs. Load Capacitance, C (at Maximum Ambient Operating ...
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... A6 A7 XTAL CLKIN CLKOUT GND A8 A9 A10 A11 A12 A13 NC MMAP NC NC PWD CONNECT REV. A ADSP-2171/ADSP-2172/ADSP-2173 128-Lead TQFP Package Pinout TOP VIEW (PINS DOWN) –45– 103 102 NC NC D23 D22 D21 D20 D19 GND D18 D17 D16 D15 D14 D13 ...
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... ADSP-2171/ADSP-2172/ADSP-2173 TQFP Pin TQFP Number Name Number 1 GND 33 2 GND 34 3 HA2/ALE 35 4 HA1 36 5 HA0 37 6 HSEL 38 7 HD5 39 8 HD4 40 9 HD3 41 10 HD2 42 11 HD1 43 12 HD0 GND XTAL 56 25 CLKIN 57 26 CLKOUT 58 27 GND A10 62 31 A11 ...
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... Metric Thin Plastic Quad Flatpack (TQFP) SEATING PLANE SYMBOL REV. A ADSP-2171/ADSP-2172/ADSP-2173 OUTLINE DIMENSIONS 128 1 TOP VIEW (PINS DOWN MILLIMETERS INCHES MIN TYP MAX MIN 1.60 0.05 0.15 0.002 1.30 1.40 1.50 0.051 15.75 16.00 16.25 0.620 13.90 14.00 14.10 0.547 12 ...
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... ADSP-2171/ADSP-2172/ADSP-2173 128 1 HA2/ALE HA1 HA0 HSEL HD5 HD4 HD3 HD2 HD1 HD0 V DD GND XTAL CLKIN CLKOUT GND A8 A9 A10 A11 A12 A13 CONNECT 128-Lead PQFP Package Pinout 128L PQFP (28MM x 28MM) TOP VIEW (PINS DOWN) –48– D23 D22 D21 ...
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... XTAL 54 23 CLKIN 55 24 CLKOUT 56 25 GND A10 60 29 A11 61 30 A12 62 31 A13 These pins MUST remain unconnected. REV. A ADSP-2171/ADSP-2172/ADSP-2173 PQFP Pin Configurations Pin PQFP Pin Name Number Name MMAP PWD 67 NC IRQ2 BMODE GND GND 74 D4 RESET HACK 77 D7 ...
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... ADSP-2171/ADSP-2172/ADSP-2173 128-Lead Metric Thin Plastic Quad Flatpack (PQFP) SEATING PLANE SYMBOL OUTLINE DIMENSIONS 128 1 TOP VIEW (PINS DOWN MILLIMETERS INCHES MIN TYP MAX MIN TYP 4.07 0.25 0.010 3.17 3.49 3.67 0.125 0.137 30.95 31.20 31.45 1.219 1.228 27.90 28.00 28.10 1 ...
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... Part Number** ADSP-2171KST-133 ADSP-2171BST-133 ADSP-2171KS-133 ADSP-2171BS-133 ADSP-2171KST-104 ADSP-2171BST-104 ADSP-2171KS-104 ADSP-2171BS-104 ADSP-2173BST-80 ADSP-2173BS-80 *Refer to section titled “Ordering Procedure for ADSP-2172 ROM Processors” for information about ordering ROM-coded parts. **S = Plastic Quad Flatpack Plastic Thin Quad Flatpack. REV. A ADSP-2171/ADSP-2172/ADSP-2173 ORDERING GUIDE* Ambient Instruction ...
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