ADSP-2191MKST-160 Analog Devices Inc, ADSP-2191MKST-160 Datasheet
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ADSP-2191MKST-160
Specifications of ADSP-2191MKST-160
Related parts for ADSP-2191MKST-160
ADSP-2191MKST-160 Summary of contents
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... PERFORMANCE FEATURES 6.25 ns Instruction Cycle Time, for up to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy to Use Algebraic Syntax Single-Cycle Instruction Execution Single-Cycle Context Switch between Two Sets of Com- putation and Memory Instructions Instruction Cache Allows Dual Operand Fetches in Every ...
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... ADSP-2191M INTEGRATION FEATURES 160K Bytes On-Chip RAM Configured as 32K Words 24-Bit Memory RAM and 32K Words 16-Bit Memory RAM Dual-Purpose 24-Bit Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-Bit Accumulators Unified Memory Space Allows Flexible Address Genera- ...
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... The ADSP-2191M is available in 144-lead LQFP and 144-ball mini-BGA packages. Fabricated in a high speed, low power, CMOS process, the ADSP-2191M operates with a 6.25 ns instruction cycle time (160 MIPS). All instructions, except single-word instructions, execute in one processor. The ADSP-2191M’s flexible architecture and comprehensive instruction set support multiple operations in parallel ...
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... The priority of each peripheral for interrupt service is determined by these assignments. There are three serial ports on the ADSP-2191M that provide a complete synchronous, full-duplex serial interface. This interface includes optional companding in hardware as well as a wide variety of framed or frameless data transmit and receive modes ...
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... A bit in each timer’s configuration register enables or disables the corresponding timer independently of the others. Memory Architecture The ADSP-2191M DSP provides 64K words of on-chip SRAM memory. This memory is divided into four 16K blocks located on memory Page 0 in the DSP’s memory map. In addition to the ...
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... I/O space. These instructions use an 18-bit address that is assembled from an 8-bit I/O page (IOPG) register and a 10-bit immediate value supplied in the instruction. Both the ADSP-219x core and a Host (through the Host Port Interface) can access I/O memory space. Boot Memory Space Boot memory space consists of one off-chip bank with 63 pages ...
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... Host Port DMA Memory DMA Host Port The ADSP-2191M’s Host port functions as a slave on the external bus of an external Host. The Host port interface lets a Host read from or write to the DSP’s memory space, boot space, or internal I/O space. Examples of Hosts include external micro- controllers, microprocessors, or ASICs ...
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... Otherwise, the Host port interface asserts ACK when it has completed the memory access successfully. DSP Serial Ports (SPORTs) The ADSP-2191M incorporates three complete synchronous serial ports (SPORT0, SPORT1, and SPORT2) for serial and multiprocessor communications. The SPORTs support the Acknowledge ...
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... UART Clock Rate Where D is the programmable divisor = 1 to 65536. Programmable Flag (PFx) Pins The ADSP-2191M has 16 bidirectional, general-purpose I/O, Programmable Flag (PF15–0) pins. The PF7–0 pins are dedicated to general-purpose I/O. The PF15–8 pins serve either as general-purpose I/O pins (if the DSP is connected to an 8-bit external data bus) or serve as DATA15– ...
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... Power-Down Core • Power-Down Core/Peripherals • Power-Down All Idle Mode When the ADSP-2191M is in Idle mode, the DSP core stops executing instructions, retains the contents of the instruction pipeline, and waits for an interrupt. The core clock and peripheral clock continue running. ...
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... Clock Signals The ADSP-2191M can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator crystal oscillator is used, the crystal should be connected across the CLKIN and XTAL pins, with two capacitors and a 1 MΩ shunt resistor connected as shown in values are dependent on crystal type and should be specified by the crystal manufacturer ...
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... OPMODE bit appropriately during runtime prior to using the corresponding peripheral. Bus Request and Bus Grant The ADSP-2191M can relinquish control of the data and ad- dress buses to an external device. When the external device requires access to the bus, it asserts the bus request (BR) signal. ...
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... The bus request feature operates at all times, even while the DSP is booting and RESET is active. The ADSP-2191M asserts the BGH pin when it is ready to start another external port access, but is held off because the bus was previously granted. This mechanism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems ...
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... In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the ADSP-219x processor family. Hardware tools include ADSP-219x PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. ...
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... I REV. A Additional Information This data sheet provides a general overview of the ADSP-2191M architecture and functionality. For detailed information on the 0.10" core architecture of the ADSP-219x family, refer to the ADSP-219x/ADSP-2191 DSP Hardware Reference. For details on the instruction set, refer to the ADSP-219x Instruction Set Reference ...
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... ADSP-2191M Table 7. Pin Function Descriptions (continued) Pin Type Function PF5 I/O/T Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5 /SPI1SEL2 I (during boot) /MSEL5 I PF4 I/O/T Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4 /SPI0SEL2 I (during boot) ...
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... Test Data Output (JTAG). Serial scan output of the boundary scan path. TRST Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after I powerup or held low for proper operation of the ADSP-2191M. The TRST pin has a 65 kΩ internal pull-down resistor. EMU O Emulation Status (JTAG) ...
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... ADSP-2191M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Internal (Core) Supply DDINT Voltage V External (I/O) Supply DDEXT Voltage V High Level Input Voltage IH V Low Level Input Voltage IL T Ambient Operating AMB Temperature Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS Parameter V High Level Output Voltage ...
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... I %Typical I DDINT DDINT-TYPICAL REV –0 +3.0 V +0.5 V DDEXT +0.5 V DDEXT Table 8, designers can estimate the ADSP-2191M’s internal power supply (V calculation beneath DDINT see Power Dissipation on Page 40. K-Grade (mA) CCLK = 160 MHz Peripheral Max Typ Max 600 µ µA 2 ...
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... ADSP-2191M TIMING SPECIFICATIONS This section contains timing information for the DSP’s external signals. Use the exact information given. Do not attempt to derive parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases ...
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... HTO HCLK PWM_OUT REV DFO HFO FLAG OUTPUT t HFI FLAG INPUT Figure 9. Programmable Flags Cycle Timing 1 32 equals (2 –1) cycles. HTO t HTO Figure 10. Timer PWM_OUT Cycle Timing –21– ADSP-2191M Min Max Min Max 32 12.5 (2 –1) cycles Unit Unit ns ...
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... – – edge of EMI clock. ACK low causes the DSP to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the ADSP-219x/ADSP-2191 DSP Hardware Reference HCLK. CTL ...
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... D15–0 WR REV HCLK t CSRS ARS t DRSAK t AKW t CDA t RDA t ADA t SDA Figure 12. External Port Read Cycle Timing –23– ADSP-2191M Min Max 0.5t –3 HCLK 0.5t –3 HCLK 0.5t –2 HCLK 3 t –2+W HCLK 0.5t –2 HCLK t HCLK t HCLK 3 t –4+W ...
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... ADSP-2191M External Port Bus Request and Grant Cycle Timing Table 14 and Figure 13 describe external port bus request and bus grant operations. Table 14. External Port Bus Request and Grant Cycle Timing 1, 2 Parameter Switching Characteristics CLKOUT High to xMS, Address, and RD/WR Disable ...
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... Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on the data bus size ( bits) and the data type ( bits). REV. A Min 1 –25– ADSP-2191M Max Unit HCLK HCLK NH ...
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... ADSP-2191M HCMS HIO LPW HALE HWR HACK (ACK MODE ) t HACK (READY MODE ) HAD15–0 ADDRE SS VALID HA16 START FIRST WORD Figure 14. Host Port ALE Mode Write Cycle Timing DATA DATA VALID V ALI LAST –26– HACK EACH BYTE HACK FIRS ADDRESS ...
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... Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on the data bus size ( bits) and the data type ( bits). REV. A Min –27– ADSP-2191M Max Unit HCLK HCLK ...
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... ADSP-2191M HCMS HIOMS HALE HWR HACK (ACK MO DE) t WHH K H HACK (READY MO DE HAD15–0 ADDRESS HA16 VALID START FIRST WORD Figure 15. Host Port ACC Mode Write Cycle Timing ALE DATA DATA VALID VALID FIRST LAST BYTE BYTE –28– HACK EACH BYT E ...
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... Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on the data bus size ( bits) and the data type ( bits). REV. A Min 12t HCLK 2 12t HCLK 1 –29– ADSP-2191M Max Unit 1 15t +t ns HCLK 15t +t ns HCLK ...
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... ADSP-2191M HCMS HIO HAL HRD HACK (ACK MODE (READY MO DE HAD15–0 ADDRESS HA16 VALID START FI RST WO RD Figure 16. Host Port ALE Mode Read Cycle Timing t t ALC DATA DATA VALID VALID FIRST LAST BYTE BYTE –30– HACK FOR EACH BYTE ...
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... Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on the data bus size ( bits) and the data type ( bits). REV. A Min 12t HCLK 2 12t HCLK 0 2.5 1 –31– ADSP-2191M Max Unit 1 15t +t ns HCLK 15t +t ns HCLK ...
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... ADSP-2191M HCMS HIO MS t ALC HALE HWR ALE R HRD t t WSH K S HACK (ACK MODE ) HACK (READY MODE ) ADDRE SS HAD15–0 HA16 VALID START WORD Figure 17. Host Port ACC Mode Read Cycle Timing DATA DATA V ALID V ALID FIRS T L AST – ...
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... If external RFSD/TFS setup to RCLK/TCLK>0.5t REV. A describe SPORT RFS Setup Before RCLK and t . DDTENFS DDTLFSE , t and t apply; otherwise t LSCK DDTLSCK DTENLSCK –33– ADSP-2191M Min Max 4 4 1.5 4 0.5t –1 HCLK 2t HCLK 13.4 4 13.4 4 0.5t –3.5 0.5t +2.5 HCLK HCLK 0 12 ...
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... ADSP-2191M DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE t SCLKIW RCLK t DFSE t HOFSE t SFSI RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT-INTERNAL CLOCK DRIVE EDGE t SCLKIW TCLK t DFSE t HOFSE t SFSI TFS t DDTI t HDTI DT NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE ...
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... HDTE/ I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t t SFSE/ I HOFSE DDTE / I DTENLFSE t HDTE/ I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t t HOFSE/ I SFSE DDTE/ I DTENLFSE t HDTE/ I 1ST BIT t DDTLFSE –35– ADSP-2191M 2ND BIT 2ND BIT ) SCLK 2ND BIT 2ND BIT ) HCLK ...
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... ADSP-2191M Serial Peripheral Interface (SPI) Port—Master Timing Table 20 and Figure 21 describe SPI port master operations. Table 20. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Switching Characteristics SPIxSEL Low to First SCLK edge (x SDSCIM t Serial Clock High Period SPICHM t Serial Clock Low Period ...
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... Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing REV SPICLS SPICLK t SPICHS DDSPID HDSPID DDSPID MSB t t HSPID SSPID MSB VALID DDSPID MSB t SSPID MSB LSB VALID –37– ADSP-2191M Min Max HCLK 2t HCLK 4t HCLK 2t HCLK 2t +4 HCLK 2t HCLK 1.6 2 HDS ...
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... ADSP-2191M Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 23 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART ...
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... System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, CLKIN, RESET MHz max. TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS REV TCK t t STAP HTA P t DTDO t SSYS t DSYS Figure 24. JTAG Port Timing –39– ADSP-2191M Min Max Unit TCK t HSYS ...
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... ADSP-2191M Output Drive Currents Figure 25 shows typical I-V characteristics for the output drivers of the ADSP-2191M. The curves represent the current drive capability of the output drivers as a function of output voltage 3.65V @ DDEXT OUTPUT CURRENT 0 V DDEXT – DDEXT OL –40 V DDEXT –60 V DDEXT – ...
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... Temperature) vs. Load Capacitance 1.5V Environmental Conditions The thermal characteristics in which the DSP is operating influence performance. Thermal Characteristics The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball Grid Array (mini-BGA) package. The ADSP-2191M is specified for an ambient temperature (T formula below. –41– ADSP-2191M (Figure 26) ...
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... ADSP-2191M – 100 150 LOAD CAPACITANCE – pF Figure 30. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) To ensure that the T data sheet specification is not exceeded, AMB a heatsink and/or an air flow source may be used. A heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive ...
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... RESET 56 HAD10 15 64 HAD11 17 RFS0 46 HAD12 18 RFS1 81 HAD13 20 RFS2 5 HAD14 21 RXD 16 HAD15 22 TCK 29 HALE 30 TCLK0 –43– ADSP-2191M Pin Pin No. Signal No. 27 TCLK1 65 28 TCLK2 47 31 TDI 75 32 TDO 74 114 TFS0 59 115 TFS1 66 116 TFS2 48 117 TMR0 43 119 TMR1 44 83 TMR2 ...
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... ADSP-2191M Table 26. 144-Lead LQFP Pins (Numerically by Pin Number) Pin Pin No. Signal No. Signal 1 D14 30 HALE HRD 2 D15 31 HWR 3 HAD0 32 4 HAD1 33 GND 5 GND 34 PF0 6 HAD2 35 PF1 7 HAD3 36 PF2 8 HAD4 37 PF3 9 HAD5 38 PF4 10 HAD6 39 PF5 11 HAD7 40 V DDEXT 12 HAD8 41 PF6 PF7 DDEXT 14 HAD9 ...
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... RCLK2 RD H6 HAD10 F1 RESET L8 HAD11 E3 H4 HAD12 F2 RFS0 J10 HAD13 G2 RFS1 A1 HAD14 F3 RFS2 A12 HAD15 G3 RXD E7 HA16 H2 TCK –45– ADSP-2191M Ball Ball No. Signal No. J1 TCLK0 J6 J3 TCLK1 M9 H1 TCLK2 K5 J2 TDI K12 K2 TDO L11 E8 TFS0 M8 D9 TFS1 J8 A9 TFS2 M5 C9 ...
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... ADSP-2191M Table 28. 144-Lead Mini-BGA Pins (Numerically by Ball Number) Ball Ball No. Signal No. Signal A1 GND C6 CLKOUT A2 D13 MS2 CLKIN C10 A6 D3 C11 A17 A7 D1 C12 A18 A8 ACK D1 HAD3 MS1 A9 D2 HAD6 BMS A10 D3 HAD5 A11 A21 D4 HAD4 A12 GND D14 D6 V DDINT B2 D15 ...
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... DETAIL A TOP VIEW (PINS DOWN) 144-Ball Mini-BGA [PBGA] (CA-144- 8.80 BSC SQ 0.80 BSC (BALL PITCH) BOTTOM VIEW DETAIL A 0.25 MIN 0.55 0.50 0.45 (BALL DIAMETER) DETAIL A –47– ADSP-2191M 20.00 BSC SQ 109 108 0.85 MIN SEATING PLANE 0.10 MAX (BALL COPLANARITY) ...
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... ADSP-2191M 1, 2 Part Number Ambient Temperature Range ADSP-2191MKST-160 0ºC to 70ºC ADSP-2191MBST-140 –40ºC to +85ºC ADSP-2191MKCA-160 0ºC to 70ºC ADSP-2191MBCA-140 –40ºC to +85º Plastic Thin Quad Flatpack (LQFP Mini Ball Grid Array (PBGA) Revision History Location 7/02—Changed from Rev Rev. A Changes to formatting only ...