ADSP-2186KST-133 Analog Devices Inc, ADSP-2186KST-133 Datasheet - Page 10

• Manufacturer Part Number: ADSP-2186KST-133
• Description: IC DSP CONTROLLER 16BIT 100LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2186KST-133

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 33.3MHz
• Non-volatile Memory: External
• On-chip Ram: 40kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 33.3MHz
• Mips: 33.3
• Device Input Clock Speed: 33.3MHz
• Ram Size: 40KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-2186
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses is done from the byte memory space to build
the word size selected. Table V shows the data formats supported
by the BDMA circuit.
BTYPE
00
01
10
11
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit BEAD
register specifies the starting address for the external byte memory
space. The 8-bit BMPAGE register specifies the starting page for
the external byte memory space. The BDIR register field selects
the direction of the transfer. The 14-bit BWCOUNT register
specifies the number of DSP words to transfer and initiates the
BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
Mode B, PMOVLAY or DMOVLAY.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory
accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.
Internal
Memory Space
Program Memory
Data Memory
Data Memory
Data Memory
Table V. BDMA Data Formats
Word Size
24
16
8
8
Alignment
Full Word
Full Word
MSBs
LSBs
Internal Memory DMA Port (IDMA Port; Host Memory Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2186. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written to while the ADSP-2186
is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.
Once the address is stored, data can then either be read from or
written to the ADSP-2186’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2186 that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Bootstrap Loading (Booting)
The ADSP-2186 has two mechanisms to allow automatic load-
ing of the internal program memory after reset. The method for
booting is controlled by the Mode A, B and C configuration bits
as shown in Table VI. These four states can be compressed into
two-state bits by allowing an IDMA boot with Mode C = 1.
However, three bits are used to ensure future compatibility with
parts containing internal program memory ROM.
BDMA Booting
When the MODE pins specify BDMA booting, the ADSP-2186
initiates a BDMA boot sequence when RESET is released.