Z8937320FSG Zilog, Z8937320FSG Datasheet - Page 47

• Manufacturer Part Number: Z8937320FSG
• Description: DSP 20MHZ 80-PQFP
• Manufacturer: Zilog
• Series: Z893x3r
• Type: Fixed Pointr

Specifications of Z8937320FSG

• Interface: SPI, 3-Wire Serial
• Clock Rate: 20MHz
• Non-volatile Memory: OTP (16 kB)
• On-chip Ram: 1kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ZiLOG
SYSTEM CLOCK GENERATOR
The System Clock can be generated from an external clock
signal, or from the internal crystal oscillator. For the latter
case, a 32-kHz crystal is used in conjunction with the in-
ternal crystal oscillator. The system clock generator in-
cludes a Phase-Locked Loop (PLL) circuit to derive a high-
frequency System Clock from the low-frequency crystal os-
cillator. The benefits of using a low-frequency crystal are
Modes of Operation
The various modes of clock operation are selected by writ-
ing to the appropriate bits and fields of the Clock Control
Register, Bank15/EXT5. The mode of operation can be
switched dynamically during program execution.
Power-up and Reset (Default)
At power-up, and following a reset or Sleep Mode Recov-
ery, System Clock Select = 0, therefore system clock =
CLKI. The XTAL Oscillator is running, so CLKI may be
provided by a crystal, as depicted, or by an external clock
(not shown). The VCO is running to minimize the time re-
quired to switch the system clock to PLL Out.
External Clock Direct
In this mode, an external clock on CLKI provides the Sys-
tem Clock. CLKO is not connected. System Clock Select
= 0. The PLL is not used. The XTAL oscillator and VCO
are both stopped to reduce power consumption.
DS000202-DSP0599
32 kHz
Off-Chip
CLKO
CLKI
LPF
On-Chip
XTAL
Osc.
PLL
Phase
Detector
LPF
PLL In
2
Figure 42. System Clock Generator
8-Bit
Clock
Divide
VCO
lower system cost, lower power consumption and lower
EMI.
The Z893x3 supports several low-power clock modes to op-
timize power consumption. Total power consumption de-
pends on System Clock frequency, and which oscillators
and peripherals are enabled.
Crystal Oscillator DIrect
In this mode of operation, the XTAL Oscillator is running,
and an external crystal provides a 32-kHz (typical) clock
at CLKI. System Clock Select = 0, so the System Clock is
the frequency at CLKI (32 kHz). This mode requires less
power than running at a high-frequency clock rate. The
VCO may be stopped to conserve even more power, or left
running for rapid switching (wake up) to a high-frequency
PLL generated clock. Whenever the PLL circuit is enabled,
Stop VCO = 0, and a software delay of 10 ms must be ob-
served before switching System Clock from CLKI to PLL
Out. As a result, the PLL has time to stabilize.
PLL Clock
An external 32-kHz crystal, together with the on-chip
XTAL oscillator, provides the PLL input. The VCO gen-
erates the System Clock. A low-pass filter must be connect-
ed to LPF as depicted. The XTAL oscillator and VCO are
both running, and System Clock = PLL Out (System Clock
Select = 1). The frequency generated by the PLL is deter-
VCO Out
16-Bit Digital Signal Processors with A/D Converter
2
2
10
11
00
01
MUX
PLL Out
CLKI
PLL Out. Sel.
Stop VCO
PLL Divisor
Stop XTAL Osc
1
0
MUX
Z89223/273/323/373
System
Clock
Select
System Clock
Clock
Control
Register
47