ADSP-2181KSTZ-160 Analog Devices Inc, ADSP-2181KSTZ-160 Datasheet
ADSP-2181KSTZ-160
Specifications of ADSP-2181KSTZ-160
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ADSP-2181KSTZ-160 Summary of contents
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... Every instruction can execute in a single processor cycle. The ADSP-2181’s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. In one processor cycle the ADSP-2181 can: • Generate the next program address • Fetch the next instruction • ...
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... ADSP-2181 evaluation board with PC monitor software plus Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low-cost, easy to use hard- ware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: • ...
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... The ADSP-2181 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2181 SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third Edition for further details. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. • ...
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... Ground Pins VDD 6 – Power Supply Pins *These ADSP-2181 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead ...
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... The CLKOUT pin may also be disabled to reduce external power dissipation. REV. D Power-Down The ADSP-2181 processor has a low power feature that lets the processor enter a very low power dormant state through Address (Hex) hardware or software control. Here is a brief list of power- down features. For detailed information about the power- down feature, refer to the ADSP-2100 Family User’ ...
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... IAD15-0 Figure 2. ADSP-2181 Basic System Configuration Clock Signals The ADSP-2181 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’ ...
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... The ADSP-2181 contains a 16K 24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. In addition, the ADSP-2181 allows the use of 8K external memory overlays. The program memory space organization is controlled by the MMAP pin and the PMOVLAY register ...
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... BDMA feature. The byte memory space Not Applicable consists of 256 pages, each of which is 16K 8. 13 LSBs of Address The byte memory space on the ADSP-2181 supports read and Between 0x0000 write operations as well as four different data formats. The byte and 0x1FFF memory uses data bits 15:8 for data ...
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... Internal Memory DMA Port (IDMA Port) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2181. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...
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... The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-2181 is ready to execute an instruction, but is stopped because the external bus is already granted to another device. The other device can re- lease the bus by deasserting bus request ...
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... DSP components statistically vary in switching characteristic and timing require- ments within published limits. Restriction: All memory strobe signals on the ADSP-2181 (RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your target system must have 10 k pull-up resistors connected when the EZ-ICE is being used ...
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... Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0–PF7 BR, CLKIN Inactive Idle refers to ADSP-2181 state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 12, 13, 14), 30% are type 2 DD and type 6, and 20% are idle instructions ...
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... The ADSP-2181 features proprietary ESD protection circuitry to dissipate high energy discharges (Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2181 has been classified as a Class 1 device. Proper ESD precautions are recommended to avoid performance degradation or loss of function- ality ...
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... ADSP-2181 Parameter Clock Signals and Reset Timing Requirements: t CLKIN Period CKI t CLKIN Width Low CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT High CKOH Control Signals Timing Requirement: RESET Width Low ...
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... PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5 Flag outputs = PFx, FL0, FL1, FL2, Flag_out4. CLKOUT FLAG OUTPUTS REV. D Min 0.25t 0.25t 5 0. FOD t FOH t IFH IRQx FI PFx t IFS Figure 9. Interrupts and Flags –15– ADSP-2181 Max + – 0. Unit ...
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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on 1 the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships. BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...
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... PMS, DMS, CMS, IOMS, BMS. CLKOUT A0–A13 DMS, PMS, BMS, IOMS, CMS REV. D Min 0 0.5t – 0.25t – 0.25t – 0.25t – 0.5t – RDA t ASR RWR CRD t t RDD RDH t AA Figure 11. Memory Read –17– ADSP-2181 Max Unit 0.5t – 0.75t – 10 0.25t + ...
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... ADSP-2181 Parameter Memory Write Switching Characteristics: Data Setup before WR High t DW Data Hold after WR High Pulsewidth Low to Data Enabled t WDE A0–A13, xMS Setup before WR Low t ASW Data Disable before Low t DDR CLKOUT High to WR Low t CWR A0–A13, xMS, Setup before WR Deasserted ...
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... FRAME DELAY 0 (MFD = 0) TFS IN ALTERNATE FRAME MODE RFS IN MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) REV. D OUT SCS SCH SCDD t SCDV t t SCDH SCDE t TDE t TDV t RDV t TDE t TDV t RDV Figure 13. Serial Ports –19– ADSP-2181 Min Max 0.25t 0.25t + SCK t SCP t SCP Unit ...
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... ADSP-2181 Parameter IDMA Address Latch Timing Requirements: t Duration of Address Latch IALP t IAD15–0 Address Setup before Address Latch End IASU t IAD15–0 Address Hold after Address Latch End IAH IACK Low before Start of Address Latch t IKA t Start of Write or Read after Address Latch End ...
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... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 4 IACK IS IWR IAD15–0 REV. D Min IDSU IDH , t . IKSU IKH t IKW t IKHW t IWP t IDH t IDSU DATA Figure 15. IDMA Write, Short Write Cycle –21– ADSP-2181 Max Unit ...
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... ADSP-2181 Parameter IDMA Write, Long Write Cycle Timing Requirements: IACK Low before Start of Write t IKW IAD15–0 Data Setup before IACK Low t IKSU IAD15–0 Data Hold after IACK Low t IKH Switching Characteristics: Start of Write to IACK Low t IKLW Start of Write to IACK High ...
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... DM read or first half of PM read. 4 Second half of PM read. IACK IS IRD IAD15–0 REV IKHR t IKR t IRP t t IKDS IRDE PREVIOUS READ DATA DATA t IRDV t IRDH Figure 17. IDMA Read, Long Read Cycle –23– ADSP-2181 Min Max 0.5t – – – IKDH t IKDD Unit ...
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... ADSP-2181 Parameter IDMA Read, Short Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read IRP Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Hold after End of Read IKDH t IAD15–0 Data Disabled after End of Read ...
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... 4.5V DD VALID FOR ALL TEMPERATURE GRADES. 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2 IDLE REFERS TO ADSP-2181 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V 3 TYPICAL POWER DISSIPATION AT 5. MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL DD MEMORY ...
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... ADSP-2181 CAPACITIVE LOADING Figures 22 and 23 show the capacitive loading characteristics of the ADSP-2181 100 150 C – Figure 22. Range of Output Rise Time vs. Load Capaci- tance, C (at Maximum Ambient Operating Temperature –2 – 100 150 C – Figure 23. Range of Output Valid Delay or Hold vs. Load Capacitance, C ...
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... ENVIRONMENTAL CONDITIONS Ambient Temperature Rating – (PD ) AMB CASE Case Temperature in C CASE PD = Power Dissipation Thermal Resistance (Case-to-Ambient Thermal Resistance (Junction-to-Ambient Thermal Resistance (Junction-to-Case Package JA JC TQFP 50 C/W 2 C/W PQFP 41 C/W 10 C/W REV C/W 31 C/W –27– ADSP-2181 ...
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... ADSP-2181 128 1 IAL PF3 PF2 PF1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP PWD IRQ2 38 128-Lead TQFP Package Pinout TOP VIEW (PINS DOWN) 39 –28– 103 ...
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... RFS1/IRQ0 89 D14 GND 90 GND DR1/FI 91 VDD SCLK1 92 GND ERESET 93 D15 RESET 94 D16 EMS 95 D17 EE 96 D18 –29– ADSP-2181 TQFP Pin Number Name 97 D19 98 D20 99 D21 100 D22 101 D23 102 GND IWR 103 IRD 104 105 IAD15 106 IAD14 107 ...
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... ADSP-2181 128 1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 A12 A13 IRQE MMAP 32 33 128-Lead PQFP Package Pinout 128L PQFP (28MM x 28MM) TOP VIEW (PINS DOWN) –30– D22 D21 ...
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... ERESET 89 D15 RESET 90 D16 EMS 91 D17 EE 92 D18 ECLK 93 D19 ELOUT 94 D20 ELIN 95 D21 EINT 96 D22 –31– ADSP-2181 PQFP Pin Number Name 97 D23 98 GND IWR 99 IRD 100 101 IAD15 102 IAD14 103 IAD13 104 IAD12 105 IAD11 106 IAD10 107 ...
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... C to +70 C ADSP-2181BST-115 – +85 C ADSP-2181KS-115 +70 C ADSP-2181BS-115 – +85 C ADSP-2181KST-133 +70 C ADSP-2181BST-133 – +85 C ADSP-2181KS-133 +70 C ADSP-2181BS-133 – +85 C ADSP-2181KST-160 +70 C ADSP-2181KS-160 + Plastic Quad Flatpack (PQFP Plastic Thin Quad Flatpack (TQFP). OUTLINE DIMENSIONS Dimensions shown in mm and (inches). 128-Lead Metric Thin Plastic Quad Flatpack (TQFP) 1 ...