ADSP-21065LKSZ-240 Analog Devices Inc, ADSP-21065LKSZ-240 Datasheet - Page 33

• Manufacturer Part Number: ADSP-21065LKSZ-240
• Description: IC DSP CONTROLLR 544KBIT 208MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21065LKSZ-240

• Interface: Host Interface, Serial Port
• Clock Rate: 60MHz
• Non-volatile Memory: External
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• No. Of Bits: 32 Bit
• Frequency: 60MHz
• Supply Voltage: 3.3V
• Embedded Interface Type: HPI, Serial
• No. Of I/o's: 12
• No. Of Mips: 66
• Supply Voltage Range: 3.13V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-21065LKSZ240; ADSP-21065LKSZ240

REV. C
TFS ("LATE", EXT.)
TFS ("LATE", INT.)
DATA RECEIVE– INTERNAL CLOCK
DATA TRANSMIT– INTERNAL CLOCK
RCLK
TCLK
RFS
TFS
DR
DT
TCLK (EXT)
TCLK (INT)
DRIVE
DRIVE
EDGE
EDGE
DT
DT
t
t
HOFSE
t
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
HOFSI
HDTI
t
DFSE
t
t
DRIVE
EDGE
DRIVE
DFSI
EDGE
DDTI
t
t
DDTIN
DDTEN
t
t
SCLKIW
SCLKIW
t
TFS, RFS, DT
t
t
TCLK, RCLK
SFSI
SFSI
SDRI
RCLK (INT)
TCLK (INT)
CLKIN
SAMPLE
SAMPLE
EDGE
EDGE
t
t
t
HFSI
HDRI
HFSI
SPORT DISABLE DELAY
FROM INSTRUCTION
Figure 20. Serial Ports
LOW TO HIGH ONLY
t
DCLK
t
DPTR
–33–
TCLK / RCLK
TCLK / RCLK
DATA RECEIVE– EXTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
RCLK
TCLK
RFS
TFS
DR
DT
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
DRIVE
DRIVE
EDGE
EDGE
t
t
t
HOFSE
HOFSE
DRIVE
DRIVE
EDGE
EDGE
HDTE
t
t
t
DFSE
DFSE
DDTTI
t
t
DDTE
DDTTE
t
t
SCLKW
SCLKW
t
t
t
SFSE
SDRE
SFSE
ADSP-21065L
SAMPLE
SAMPLE
EDGE
EDGE
t
t
t
HFSE
HDRE
HFSE