XC95288XV-10CS280C Xilinx Inc, XC95288XV-10CS280C Datasheet

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XC95288XV-10CS280C

Manufacturer Part Number
XC95288XV-10CS280C
Description
IC CPLD 2.5V ISP 280-CSP
Manufacturer
Xilinx Inc
Series
XC9500XVr

Specifications of XC95288XV-10CS280C

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
2.37 V ~ 2.62 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
288
Number Of Gates
6400
Number Of I /o
192
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
280-CSBGA
Voltage
2.5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
XC95288XV10CS280C

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Price
Part Number:
XC95288XV-10CS280C
Manufacturer:
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XC95288XV-10CS280C
Manufacturer:
XILINX
Quantity:
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u
DS050 (v3.0) June 25, 2007
Note: This product is being discontinued. You cannot
order parts after May 14, 2008. Xilinx recommends replac-
ing XC95288XV devices with equivalent XC95288XL
devices in all designs as soon as possible. Recommended
replacements are pin compatible, however require a V
change to 3.3V, and a recompile of the design file. In addi-
tion, there is no 1.8V I/O support, and only one output bank
is supported. See
continuation, including device replacement recomendations
for the XC95288XV CPLD.
Features
Description
The XC95288XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns.
DS050 (v3.0) June 25, 2007
Product Specification
© 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
288 macrocells with 6,400 usable gates
Available in small footprint packages
-
-
-
-
Optimized for high-performance 2.5V systems
-
-
Advanced system features
-
-
-
-
-
-
-
-
-
-
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
-
144-pin TQFP (117 user I/O pins)
208-pin PQFP (168 user I/O pins)
280-pin CSP (192 user I/O pins)
256-pin FBGA (192 user I/O pins)
Low power operation
Multi-voltage operation
In-system programmable
Four separate output banks
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
20 year data retention
ESD protection exceeding 2,000V
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
XCN07010
R
for details regarding this dis-
0
0
www.xilinx.com
CC
5
XC95288XV High-Performance
CPLD
Product Specification
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
used:
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. P
tance driven, so it is handled by I = CVf. I
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
I
I
PT
where:
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
value varies with the design application and should be veri-
fied during normal system operation.
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
CCINT
CCINT
LP
MC
MC
PT
PT
f
MC
frequently a good estimate
MAX
+ 0.171) + 0.04(MC
(mA) = MC
(taken from simulation) is:
HS
LP
P
HS
LP
TOG
TOTAL
= max clocking frequency in the device
= average p-terms used over low power macrocell
= average p-terms used per high speed macrocell
= #macrocells used in low power mode
= # macrocells used in high speed mode
= % macrocells toggling on each clock (12% is
= P
HS
IO
INT
(0.122 X PT
is a strong function of the load capaci-
+ P
HS
IO
CC
= I
, the following equation may be
+ MC
CCINT
HS
LP
+ 0.238) + MC
) x f
x V
Figure 1
MAX
CCINT
CCINT
x MC
+ P
LP
shows the
is another
TOG
IO
(0.042 x
CC
1

Related parts for XC95288XV-10CS280C

XC95288XV-10CS280C Summary of contents

Page 1

... ESD protection exceeding 2,000V Description The XC95288XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with propagation delays of 6 ns. © 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...

Page 2

... XC95288XV High-Performance CPLD application note XAPP361, “Planning for High Speed XC9500XV Designs.” 450 400 350 300 250 200 150 100 100 C lock F requency ( Figure 1: Typical I vs. Frequency for XC95288XV CC 2 150 200 250 DS050_01_041405 www.xilinx.com R DS050 (v3.0) June 25, 2007 Product Specification ...

Page 3

... I/O/GCK 1 I/O/GSR 4 I/O/GTS (Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.) DS050 (v3.0) June 25, 2007 Product Specification JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95288XV Architecture www.xilinx.com XC95288XV High-Performance CPLD 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells ...

Page 4

... Table 1: IOSTANDARD Options IOSTANDARD V CCIO LVTTL 3.3V LVCMOS2 2.5V X25TO18 1.8V The XC95288XV CPLD features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage for output drivers ...

Page 5

... MHz V = GND, No load 1.0 MHz XC95288XV-6 Min Max - 6.0 4 3.8 - 208 1 6.8 - 4.5 - 4.5 - 8.4 - 8.4 www.xilinx.com XC95288XV High-Performance CPLD Min Max Units 20 - Years 1,000 - Cycles 2,000 - Volts Min Max 2.4 - 2 CCIO - 0.4 - 0.4 - 0.4 - ±10 - ±10 - ±150 ...

Page 6

... XC95288XV High-Performance CPLD Symbol Parameter T GSR to output valid AO T P-term S/R to output valid PAO T GCK pulse width (High or Low) WLH T P-term clock pulse width (High or Low) PLH T Asynchronous preset/reset pulse width APRPW (High or Low) 6 XC95288XV-6 XC95288XV-7 Min Max Min Max - 10 ...

Page 7

... XC95288XV High-Performance CPLD 320Ω 360Ω 250Ω 660Ω 10KΩ 14KΩ DS050_03_110101 XC95288XV-7 XC95288XV-10 Min Max Min Max Units - 2.3 - 3.5 - 1 ...

Page 8

... XC95288XV High-Performance CPLD XC95288XV I/O Pins Function Macro- Block cell TQ144 PQ208 FG256 CS280 Notes: 1. Global control pin 8 BScan Function Order Bank Block - - 861 - 3 K2 858 855 852 - 3 K4 849 846 843 - 3 L2 840 837 834 831 828 825 - 3 M3 822 ...

Page 9

... R XC95288XV I/O Pins (continued) Function Macro- Block cell TQ144 PQ208 FG256 CS280 (1) ( 135 197 136 198 137 199 138 200 139 201 140 202 203 142 205 B4 (1) ( 143 206 208 Notes: 1. Global control pin DS050 (v3.0) June 25, 2007 Product Specification ...

Page 10

... XC95288XV High-Performance CPLD XC95288XV I/O Pins (continued) Function Macro- Block cell TQ144 PQ208 FG256 CS280 T10 M10 R10 T11 117 170 B11 10 3 118 171 D11 119 173 A11 10 6 120 174 D10 121 175 B10 E12 10 10 124 178 F12 ...

Page 11

... R XC95288XV I/O Pins (continued) Function Macro- Block cell TQ144 PQ208 FG256 CS280 103 P13 106 P15 107 N14 109 R16 110 N15 M15 111 M13 112 P16 113 N16 114 M14 115 L15 116 L13 144 F15 14 3 100 145 E15 ...

Page 12

... XC95288XV High-Performance CPLD XC95288XV Global, JTAG and Power Pins Pin Type TQ144 I/O/GCK1 30 I/O/GCK2 32 I/O/GCK3 38 I/O/GTS1 5 I/O/GTS2 6 I/O/GTS3 2 I/O/GTS4 3 I/O/GSR 143 TCK 67 TDI 63 (1) TDO 122 TMS 65 V 2.5V 8, 42, 84, 141 CCINT V 37 CCIO1 V 1 CCIO2 V 55, 73 CCIO3 V 109, 127 CCIO4 ...

Page 13

... XC95288XV-7CS280C 7.5 ns XC95288XV-7TQ144I 7.5 ns XC95288XV-7PQ208I 7.5 ns XC95288XV-7FG256I 7.5 ns XC95288XV-7CS280I 7.5 ns XC95288XV-10TQ144C 10 ns XC95288XV-10PQ208C 10 ns XC95288XV-10FG256C 10 ns XC95288XV-10CS280C 10 ns XC95288XV-10TQ144I 10 ns XC95288XV-10PQ208I 10 ns XC95288XV-10FG256I 10 ns XC95288XV-10CS280I 10 ns Notes Commercial 0° to +70° Industrial Some packages available in Pb-free option. See DS050 (v3.0) June 25, 2007 ...

Page 14

... XC95288XV High-Performance CPLD Revision History Date Version 09/28/98 1.0 Original creation of data sheet. 12/10/98 1.1 Revision of tables. 2/5/99 1.2 Updated pinouts to reflect BG256 (replaces BG352). 6/7/99 1.3 Add -7 speed and CS280 package. 4/11/00 1.4 Updated AC specifications, added bank information to pinout tables. ...

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