XC95216-10HQ208C Xilinx Inc, XC95216-10HQ208C Datasheet

no-image

XC95216-10HQ208C

Manufacturer Part Number
XC95216-10HQ208C
Description
IC CPLD 216 MCELL C-TEMP 208HQFP
Manufacturer
Xilinx Inc
Series
XC9500r
Datasheets

Specifications of XC95216-10HQ208C

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
12
Number Of Macrocells
216
Number Of Gates
4800
Number Of I /o
166
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Voltage
5V
Memory Type
FLASH
Case
QFP208
Dc
00+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC95216-10HQ208C
Manufacturer:
MICRON
Quantity:
1 000
Part Number:
XC95216-10HQ208C
Manufacturer:
XILINX
Quantity:
235
Part Number:
XC95216-10HQ208C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC95216-10HQ208C
Manufacturer:
XILINX
0
Part Number:
XC95216-10HQ208C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DS068 (v4.4) June 25, 2007
Note: The 352-pin BGA packages are being discontin-
ued for XC95216 devices. You cannot order these pack-
ages after May 14, 2008. Xilinx recommends replacing
XC95216 in 352-pin BGA packages with XC95288 devices
in 352-pin BGA packages in all designs as soon as possi-
ble. Recommended replacements are pin compatible, but
require recompiling of the design file. See
details regarding this discontinuation, including device
replacement recomendations for the XC95216 352-pin
BGA CPLD.
Features
DS068 (v4.4) June 25, 2007
Product Specification
© 1996-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
10 ns pin-to-pin logic delays on all pins
f
216 macrocells with 4,800 usable gates
Up to 166 user I/O pins
5V in-system programmable
-
-
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
-
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of more than one
XC9500 concurrently
Available 160-pin PQFP, 352-pin BGA, and 208-pin
HQFP packages (Note: 352-pin BGA packages are
being discontinued for this device)
CNT
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables,
set and reset signals
to 111 MHz
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
XCN07010
0
0
www.xilinx.com
for
5
XC95216 In-System
Programmable CPLD
Product Specification
Description
The XC95216 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 4,800 usable gates with
propagation delays of 10 ns. See
ture overview.
Power Management
Power dissipation can be reduced in the XC95216 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
Where:
Figure 1
device.
CC
(mA) = MC
(360)
Figure 1: Typical I
MC
MC
MC = Total number of macrocells used
f = Clock frequency (MHz)
600
400
200
0
HP
LP
shows a typical calculation for the XC95216
= Macrocells in low-power mode
= Macrocells in high-performance mode
HP
(1.7) + MC
Clock Frequency (MHz)
CC
vs. Frequency for XC95216
LP
50
(0.9) + MC (0.006 mA/MHz) f
Figure 2
for the architec-
DS068_01_110101
100
(500)
(340)
1

Related parts for XC95216-10HQ208C

XC95216-10HQ208C Summary of contents

Page 1

... See XCN07010 for ture overview. Power Management Power dissipation can be reduced in the XC95216 by con- figuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ...

Page 2

... I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function block outputs (indicated by the bold line) drive the I/O blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95216 Architecture www.xilinx.com 36 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...

Page 3

... –3 Max GND Max GND GND 1.0 MHz V = GND, No load 1.0 MHz www.xilinx.com XC95216 In-System Programmable CPLD Value –0.5 to 7.0 –0 0.5 CC –0 0.5 CC –65 to +150 +150 Min Max o C 4.75 5. 4.5 5 4.75 5. 4.5 5.5 3.0 3.6 0 0.80 2 0.5 CCINT ...

Page 4

... XC95216 In-System Programmable CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO (1) f 16-bit counter frequency CNT (2) f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input ...

Page 5

... T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW Notes multiplied by the span of the function as defined in the XC9500 family data sheet. PTA DS068 (v4.4) June 25, 2007 Product Specification XC95216 In-System Programmable CPLD XC95216-10 XC95216-15 Min Max Min - 3 2 6.0 ...

Page 6

... Notes: 1. Global control pin. 2. 352-pin BGA package is being discontinued for the XC95216. 6 BScan Function Macro- (2) Order Block cell – 645 3 M25 642 3 M26 639 3 N26 636 3 N25 633 3 P23 630 3 – 627 3 P24 624 3 R26 621 ...

Page 7

... Notes: 1. Global control pin. 2. 352-pin BGA package is being discontinued for the XC95216. DS068 (v4.4) June 25, 2007 Product Specification BScan Function Macro- (2) Order Block cell – 429 7 AE22 426 7 AE21 423 ...

Page 8

... Notes: 1. Global control pin. 2. 352-pin BGA package is being discontinued for the XC95216. 8 BScan Function Macro- (2) Order Block cell – 213 11 AD7 210 11 AE5 207 11 AD4 204 11 AC7 ...

Page 9

... R XC95216 Global, JTAG and Power Pins Pin Type PQ160 I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS V 5V 10,46,94,157 CCINT V 3.3V/5V 1,41,61,81,121,141 CCIO GND 20, 31, 40, 51, 70, 80, 99, 100, 110, 120, 127, 137, 160 No Connects DS068 (v4.4) June 25, 2007 ...

Page 10

... XC95216 In-System Programmable CPLD Device Part Marking and Ordering Combination Information Operating Range Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC95216-10PQ160C 10 ns XC95216-10PQG160C 10 ns XC95216-10HQ208C 10 ns XC95216-10BG352C 10 ns XC95216-10PQ160I 10 ns XC95216-10PQG160I 10 ns XC95216-10HQ208I 10 ns XC95216-10BG352I 10 ns XC95216-15PQ160C 15 ns XC95216-15PQG160C ...

Page 11

... Updated Package Device Marking Pin 1 orientation. 04/15/05 4.2 Added asynchronous preset/reset pulse width specification (T 04/03/06 4.3 Added Warranty Disclaimer. Added Pb-Free package ordering information. 06/25/07 4.4 Discontinuance of BG352 and BGG252 packages. DS068 (v4.4) June 25, 2007 Product Specification XC95216 In-System Programmable CPLD Revision www.xilinx.com ) APRPW 11 ...

Related keywords